330d5fd5be
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by GigaDevice, which features pin-to-pin package compatibility with STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds CAN support. Currently the code mainly targets GD32F130 and F150 chips. Some register are different between F130/150 and F170/190, just like the difference between STM32F1 Performance line and Connectivity line. From the perspective of registers and memory map, GD32F1X0 seems like a mixture between STM32F1 and STM32F0 (because it is designed to be pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of code are shared between STM32 and GD32, and these code are specially processed to include the GD32 headers instead of STM32 headers when meet GD32F1X0. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Karl Palsson <karlp@tweak.net.au> gd32/rcc.[ch] are forks of stm32f1/rcc gd32/flash.[ch] are forks of stm32f0/flash No attempts at deduplicating this have been done at this stage. We can see where they move in the future.
61 lines
2.3 KiB
C
61 lines
2.3 KiB
C
/* This file is part of the libopencm3 project.
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*
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* It was generated by the irq2nvic_h script.
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*
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* These definitions bend every interrupt handler that is defined CMSIS style
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* to the weak symbol exported by libopencm3.
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*/
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#define WWDG_IRQHandler wwdg_isr
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#define PVD_IRQHandler pvd_isr
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#define RTC_IRQHandler rtc_isr
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#define FLASH_IRQHandler flash_isr
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#define RCC_IRQHandler rcc_isr
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#define EXTI0_1_IRQHandler exti0_1_isr
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#define EXTI2_3_IRQHandler exti2_3_isr
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#define EXTI4_15_IRQHandler exti4_15_isr
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#define TSC_IRQHandler tsc_isr
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#define DMA_CHANNEL1_IRQHandler dma_channel1_isr
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#define DMA_CHANNEL2_3_IRQHandler dma_channel2_3_isr
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#define DMA_CHANNEL4_5_IRQHandler dma_channel4_5_isr
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#define ADC_COMP_IRQHandler adc_comp_isr
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#define TIM1_BRK_UP_TRG_COM_IRQHandler tim1_brk_up_trg_com_isr
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#define TIM1_CC_IRQHandler tim1_cc_isr
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#define TIM2_IRQHandler tim2_isr
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#define TIM3_IRQHandler tim3_isr
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#define TIM6_DAC_IRQHandler tim6_dac_isr
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#define RESERVED0_IRQHandler reserved0_isr
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#define TIM14_IRQHandler tim14_isr
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#define TIM15_IRQHandler tim15_isr
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#define TIM16_IRQHandler tim16_isr
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#define TIM17_IRQHandler tim17_isr
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#define I2C1_EV_IRQHandler i2c1_ev_isr
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#define I2C2_EV_IRQHandler i2c2_ev_isr
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#define SPI1_IRQHandler spi1_isr
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#define SPI2_IRQHandler spi2_isr
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#define USART1_IRQHandler usart1_isr
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#define USART2_IRQHandler usart2_isr
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#define RESERVED1_IRQHandler reserved1_isr
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#define CEC_CAN_IRQHandler cec_can_isr
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#define RESERVED2_IRQHandler reserved2_isr
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#define I2C1_ER_IRQHandler i2c1_er_isr
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#define RESERVED3_IRQHandler reserved3_isr
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#define I2C2_ER_IRQHandler i2c2_er_isr
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#define I2C3_EV_IRQHandler i2c3_ev_isr
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#define I2C3_ER_IRQHandler i2c3_er_isr
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#define USB_LP_IRQHandler usb_lp_isr
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#define USB_HP_IRQHandler usb_hp_isr
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#define RESERVED4_IRQHandler reserved4_isr
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#define RESERVED5_IRQHandler reserved5_isr
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#define RESERVED6_IRQHandler reserved6_isr
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#define USB_WAKEUP_IRQHandler usb_wakeup_isr
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#define RESERVED7_IRQHandler reserved7_isr
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#define RESERVED8_IRQHandler reserved8_isr
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#define RESERVED9_IRQHandler reserved9_isr
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#define RESERVED10_IRQHandler reserved10_isr
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#define RESERVED11_IRQHandler reserved11_isr
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#define DMA_CHANNEL6_7_IRQHandler dma_channel6_7_isr
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#define RESERVED12_IRQHandler reserved12_isr
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#define RESERVED13_IRQHandler reserved13_isr
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#define SPI3_IRQHandler spi3_isr
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