6887628eaa
Memory map is now completely freed and rebuilt in the separate attach function. It was previoulsy split beween probe and attach and never released, causing problems when reattaching to the same target.
551 lines
15 KiB
C
551 lines
15 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2015, 2017, 2018 Uwe Bonnes
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* Written by Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements STM32L4 target specific functions for detecting
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* the device, providing the XML memory map and Flash memory programming.
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*
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* On L4, flash and options are written in DWORDs (8-Byte) only.
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*
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* References:
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* RM0351 STM32L4x5 and STM32L4x6 advanced ARM®-based 32-bit MCUs Rev. 5
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* RM0394 STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxxx advanced
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* ARM®-based 32-bit MCUs Rev.3
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* RM0432 STM32L4Rxxx and STM32L4Sxxx advanced Arm®-based 32-bit MCU. Rev 1
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*
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*
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*/
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#include "general.h"
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#include "target.h"
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#include "target_internal.h"
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#include "cortexm.h"
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static bool stm32l4_cmd_erase_mass(target *t);
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static bool stm32l4_cmd_erase_bank1(target *t);
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static bool stm32l4_cmd_erase_bank2(target *t);
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static bool stm32l4_cmd_option(target *t, int argc, char *argv[]);
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const struct command_s stm32l4_cmd_list[] = {
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{"erase_mass", (cmd_handler)stm32l4_cmd_erase_mass, "Erase entire flash memory"},
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{"erase_bank1", (cmd_handler)stm32l4_cmd_erase_bank1, "Erase entire bank1 flash memory"},
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{"erase_bank2", (cmd_handler)stm32l4_cmd_erase_bank2, "Erase entire bank2 flash memory"},
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{"option", (cmd_handler)stm32l4_cmd_option, "Manipulate option bytes"},
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{NULL, NULL, NULL}
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};
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static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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static int stm32l4_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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/* Flash Program ad Erase Controller Register Map */
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE+0x00)
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#define FLASH_KEYR (FPEC_BASE+0x08)
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#define FLASH_OPTKEYR (FPEC_BASE+0x0c)
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#define FLASH_SR (FPEC_BASE+0x10)
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#define FLASH_CR (FPEC_BASE+0x14)
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#define FLASH_OPTR (FPEC_BASE+0x20)
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//#define FLASH_OPTCR (FPEC_BASE+0x14)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_MER1 (1 << 2)
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#define FLASH_CR_PAGE_SHIFT 3
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#define FLASH_CR_BKER (1 << 11)
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#define FLASH_CR_MER2 (1 << 15)
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_OPTSTRT (1 << 17)
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#define FLASH_CR_FSTPG (1 << 18)
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#define FLASH_CR_EOPIE (1 << 24)
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#define FLASH_CR_ERRIE (1 << 25)
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#define FLASH_CR_OBL_LAUNCH (1 << 27)
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#define FLASH_CR_OPTLOCK (1 << 30)
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#define FLASH_CR_LOCK (1 << 31)
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#define FLASH_SR_EOP (1 << 0)
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#define FLASH_SR_OPERR (1 << 1)
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#define FLASH_SR_PROGERR (1 << 3)
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#define FLASH_SR_WRPERR (1 << 4)
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#define FLASH_SR_PGAERR (1 << 5)
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#define FLASH_SR_SIZERR (1 << 6)
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#define FLASH_SR_PGSERR (1 << 7)
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#define FLASH_SR_MSERR (1 << 8)
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#define FLASH_SR_FASTERR (1 << 9)
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#define FLASH_SR_RDERR (1 << 14)
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#define FLASH_SR_OPTVERR (1 << 15)
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#define FLASH_SR_ERROR_MASK 0xC3FA
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#define FLASH_SR_BSY (1 << 16)
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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#define OPTKEY1 0x08192A3B
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#define OPTKEY2 0x4C5D6E7F
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#define SR_ERROR_MASK 0xF2
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/* Used in STM32L47*/
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#define OR_DUALBANK (1 << 21)
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/* Used in STM32L47R*/
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#define OR_DB1M (1 << 21)
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#define OR_DBANK (1 << 22)
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#define DBGMCU_CR(dbgmcureg) (dbgmcureg + 0x04)
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#define DBGMCU_CR_DBG_SLEEP (0x1U << 0U)
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#define DBGMCU_CR_DBG_STOP (0x1U << 1U)
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#define DBGMCU_CR_DBG_STANDBY (0x1U << 2U)
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enum {
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STM32G0_DBGMCU_IDCODE_PHYS = 0x40015800,
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STM32L4_DBGMCU_IDCODE_PHYS = 0xe0042000,
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};
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#define FLASH_SIZE_REG 0x1FFF75E0
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struct stm32l4_flash {
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struct target_flash f;
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uint32_t bank1_start;
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};
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enum ID_STM32L4 {
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ID_STM32L41 = 0x464u, /* RM0394, Rev.4 */
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ID_STM32L43 = 0x435u, /* RM0394, Rev.4 */
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ID_STM32L45 = 0x462u, /* RM0394, Rev.4 */
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ID_STM32L47 = 0x415u, /* RM0351, Rev.5 */
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ID_STM32L49 = 0x461u, /* RM0351, Rev.5 */
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ID_STM32L4R = 0x470u, /* RM0432, Rev.5 */
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ID_STM32G07 = 0x460u, /* RM0444/454, Rev.1 */
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};
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enum FAM_STM32L4 {
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FAM_STM32L4xx = 1,
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FAM_STM32L4Rx = 2,
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FAM_STM32G0x = 3,
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FAM_STM32WBxx = 4,
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};
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#define DUAL_BANK 0x80u
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#define RAM_COUNT_MSK 0x07u
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struct stm32l4_info {
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char designator[10];
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uint16_t sram1;
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uint16_t sram2;
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uint16_t sram3;
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enum ID_STM32L4 idcode;
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enum FAM_STM32L4 family;
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uint8_t flags;
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};
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struct stm32l4_info const L4info[] = {
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{
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.idcode = ID_STM32L41,
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.family = FAM_STM32L4xx,
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.designator = "STM32L41x",
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.sram1 = 32,
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.sram2 = 8,
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.flags = 2,
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},
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{
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.idcode = ID_STM32L43,
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.family = FAM_STM32L4xx,
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.designator = "STM32L43x",
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.sram1 = 48,
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.sram2 = 16,
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.flags = 2,
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},
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{
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.idcode = ID_STM32L45,
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.family = FAM_STM32L4xx,
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.designator = "STM32L45x",
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.sram1 = 128,
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.sram2 = 32,
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.flags = 2,
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},
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{
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.idcode = ID_STM32L47,
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.family = FAM_STM32L4xx,
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.designator = "STM32L47x",
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.sram1 = 96,
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.sram2 = 32,
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.flags = 2 | DUAL_BANK,
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},
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{
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.idcode = ID_STM32L49,
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.family = FAM_STM32L4xx,
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.designator = "STM32L49x",
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.sram1 = 256,
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.sram2 = 64,
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.flags = 2 | DUAL_BANK,
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},
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{
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.idcode = ID_STM32L4R,
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.family = FAM_STM32L4Rx,
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.designator = "STM32L4Rx",
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.sram1 = 192,
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.sram2 = 64,
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.sram3 = 384,
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.flags = 3 | DUAL_BANK,
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},
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{
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.idcode = ID_STM32G07,
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.family = FAM_STM32G0x,
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.designator = "STM32G07",
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.sram1 = 36,
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.flags = 1,
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},
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{
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/* Terminator */
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.idcode = 0,
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},
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};
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/* Retrieve chip basic information, just add to the vector to extend */
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static struct stm32l4_info const * stm32l4_get_chip_info(uint32_t idcode) {
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struct stm32l4_info const *p = L4info;
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while (p->idcode && (p->idcode != idcode))
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p++;
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return p;
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}
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static void stm32l4_add_flash(target *t,
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uint32_t addr, size_t length, size_t blocksize,
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uint32_t bank1_start)
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{
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struct stm32l4_flash *sf = calloc(1, sizeof(*sf));
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struct target_flash *f = &sf->f;
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f->start = addr;
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f->length = length;
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f->blocksize = blocksize;
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f->erase = stm32l4_flash_erase;
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f->write = stm32l4_flash_write;
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f->buf_size = 2048;
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f->erased = 0xff;
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sf->bank1_start = bank1_start;
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target_add_flash(t, f);
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}
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static bool stm32l4_attach(target *t)
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{
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if (!cortexm_attach(t))
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return false;
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/* Retrive chip information, no need to check return */
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struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
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uint32_t idcodereg = (chip->family == FAM_STM32G0x)
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? STM32G0_DBGMCU_IDCODE_PHYS
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: STM32L4_DBGMCU_IDCODE_PHYS;
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/* Save DBGMCU_CR to restore it when detaching*/
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uint32_t dbgmcu_cr = target_mem_read32(t, DBGMCU_CR(idcodereg));
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t->target_storage = dbgmcu_cr;
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/* Enable debugging during all low power modes*/
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target_mem_write32(t, DBGMCU_CR(idcodereg), DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_DBG_STOP);
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/* Free previously loaded memory map */
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target_mem_map_free(t);
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/* Add RAM to memory map */
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if (chip->family == FAM_STM32G0x) {
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target_add_ram(t, 0x20000000, chip->sram1 << 10);
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} else {
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target_add_ram(t, 0x10000000, chip->sram2 << 10);
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/* All L4 beside L47 alias SRAM2 after SRAM1.*/
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uint32_t ramsize = (t->idcode == ID_STM32L47)?
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chip->sram1 : (chip->sram1 + chip->sram2 + chip->sram3);
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target_add_ram(t, 0x20000000, ramsize << 10);
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}
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/* Add the flash to memory map. */
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uint32_t size = target_mem_read16(t, FLASH_SIZE_REG);
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uint32_t options = target_mem_read32(t, FLASH_OPTR);
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if (chip->family == FAM_STM32L4Rx) {
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/* rm0432 Rev. 2 does not mention 1 MB devices or explain DB1M.*/
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if (options & OR_DBANK) {
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stm32l4_add_flash(t, 0x08000000, 0x00100000, 0x1000, 0x08100000);
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stm32l4_add_flash(t, 0x08100000, 0x00100000, 0x1000, 0x08100000);
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} else
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stm32l4_add_flash(t, 0x08000000, 0x00200000, 0x2000, -1);
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} else if (chip->flags & DUAL_BANK) {
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if (options & OR_DUALBANK) {
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uint32_t banksize = size << 9;
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stm32l4_add_flash(t, 0x08000000 , banksize, 0x0800, 0x08000000 + banksize);
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stm32l4_add_flash(t, 0x08000000 + banksize, banksize, 0x0800, 0x08000000 + banksize);
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} else {
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uint32_t banksize = size << 10;
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stm32l4_add_flash(t, 0x08000000 , banksize, 0x0800, -1);
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}
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} else
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stm32l4_add_flash(t, 0x08000000, size << 10, 0x800, -1);
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/* Clear all errors in the status register. */
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target_mem_write32(t, FLASH_SR, target_mem_read32(t, FLASH_SR));
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return true;
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}
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static void stm32l4_detach(target *t)
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{
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/*reverse all changes to DBGMCU_CR*/
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uint32_t idcodereg = STM32L4_DBGMCU_IDCODE_PHYS;
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if (t->idcode == ID_STM32G07)
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idcodereg = STM32G0_DBGMCU_IDCODE_PHYS;
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target_mem_write32(t, DBGMCU_CR(idcodereg), t->target_storage);
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cortexm_detach(t);
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}
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bool stm32l4_probe(target *t)
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{
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uint32_t idcode_reg = STM32L4_DBGMCU_IDCODE_PHYS;
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ADIv5_AP_t *ap = cortexm_ap(t);
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if (ap->dp->idcode == 0x0BC11477)
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idcode_reg = STM32G0_DBGMCU_IDCODE_PHYS;
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uint32_t idcode = target_mem_read32(t, idcode_reg) & 0xfff;
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struct stm32l4_info const *chip = stm32l4_get_chip_info(idcode);
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if( !chip->idcode ) /* Not found */
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return false;
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t->idcode = idcode;
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t->driver = chip->designator;
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t->attach = stm32l4_attach;
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t->detach = stm32l4_detach;
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target_add_commands(t, stm32l4_cmd_list, chip->designator);
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return true;
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}
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static void stm32l4_flash_unlock(target *t)
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{
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if (target_mem_read32(t, FLASH_CR) & FLASH_CR_LOCK) {
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/* Enable FPEC controller access */
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target_mem_write32(t, FLASH_KEYR, KEY1);
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target_mem_write32(t, FLASH_KEYR, KEY2);
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}
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}
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static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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{
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target *t = f->t;
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uint16_t sr;
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uint32_t bank1_start = ((struct stm32l4_flash *)f)->bank1_start;
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uint32_t page;
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uint32_t blocksize = f->blocksize;
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stm32l4_flash_unlock(t);
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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/* Fixme: OPTVER always set after reset! Wrong option defaults?*/
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target_mem_write32(t, FLASH_SR, target_mem_read32(t, FLASH_SR));
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page = (addr - 0x08000000) / blocksize;
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while(len) {
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uint32_t cr;
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cr = FLASH_CR_PER | (page << FLASH_CR_PAGE_SHIFT );
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if (addr >= bank1_start)
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cr |= FLASH_CR_BKER;
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/* Flash page erase instruction */
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target_mem_write32(t, FLASH_CR, cr);
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/* write address to FMA */
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cr |= FLASH_CR_STRT;
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target_mem_write32(t, FLASH_CR, cr);
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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len -= blocksize;
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addr += blocksize;
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page++;
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}
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/* Check for error */
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sr = target_mem_read32(t, FLASH_SR);
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if(sr & FLASH_SR_ERROR_MASK)
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return -1;
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return 0;
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}
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static int stm32l4_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len)
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{
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target *t = f->t;
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target_mem_write32(t, FLASH_CR, FLASH_CR_PG);
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target_mem_write(t, dest, src, len);
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/* Wait for completion or an error */
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uint32_t sr;
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do {
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sr = target_mem_read32(t, FLASH_SR);
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if (target_check_error(t)) {
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DEBUG("stm32l4 flash write: comm error\n");
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return -1;
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}
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} while (sr & FLASH_SR_BSY);
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if(sr & FLASH_SR_ERROR_MASK) {
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DEBUG("stm32l4 flash write error: sr 0x%" PRIu32 "\n", sr);
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return -1;
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}
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return 0;
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}
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static bool stm32l4_cmd_erase(target *t, uint32_t action)
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{
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stm32l4_flash_unlock(t);
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/* Erase time is 25 ms. No need for a spinner.*/
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/* Flash erase action start instruction */
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target_mem_write32(t, FLASH_CR, action);
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target_mem_write32(t, FLASH_CR, action | FLASH_CR_STRT);
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) {
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if(target_check_error(t)) {
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return false;
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}
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}
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/* Check for error */
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uint16_t sr = target_mem_read32(t, FLASH_SR);
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if (sr & FLASH_SR_ERROR_MASK)
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return false;
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return true;
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}
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static bool stm32l4_cmd_erase_mass(target *t)
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{
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return stm32l4_cmd_erase(t, FLASH_CR_MER1 | FLASH_CR_MER2);
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}
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static bool stm32l4_cmd_erase_bank1(target *t)
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{
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return stm32l4_cmd_erase(t, FLASH_CR_MER1);
|
|
}
|
|
|
|
static bool stm32l4_cmd_erase_bank2(target *t)
|
|
{
|
|
return stm32l4_cmd_erase(t, FLASH_CR_MER2);
|
|
}
|
|
|
|
static const uint8_t l4_i2offset[9] = {
|
|
0x20, 0x24, 0x28, 0x2c, 0x30, 0x44, 0x48, 0x4c, 0x50
|
|
};
|
|
|
|
static const uint8_t g0_i2offset[7] = {
|
|
0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38
|
|
};
|
|
|
|
static bool stm32l4_option_write(
|
|
target *t,const uint32_t *values, int len, const uint8_t *i2offset)
|
|
{
|
|
tc_printf(t, "Device will lose connection. Rescan!\n");
|
|
stm32l4_flash_unlock(t);
|
|
target_mem_write32(t, FLASH_OPTKEYR, OPTKEY1);
|
|
target_mem_write32(t, FLASH_OPTKEYR, OPTKEY2);
|
|
while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
|
|
if(target_check_error(t))
|
|
return true;
|
|
for (int i = 0; i < len; i++)
|
|
target_mem_write32(t, FPEC_BASE + i2offset[i], values[i]);
|
|
target_mem_write32(t, FLASH_CR, FLASH_CR_OPTSTRT);
|
|
while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
|
|
if(target_check_error(t))
|
|
return true;
|
|
target_mem_write32(t, FLASH_CR, FLASH_CR_OBL_LAUNCH);
|
|
while (target_mem_read32(t, FLASH_CR) & FLASH_CR_OBL_LAUNCH)
|
|
if(target_check_error(t))
|
|
return true;
|
|
target_mem_write32(t, FLASH_CR, FLASH_CR_LOCK);
|
|
return false;
|
|
}
|
|
|
|
/* Chip L43X/mask L43x/def L47x/mask L47x/def
|
|
* L49x/mask L49x/def
|
|
* Option
|
|
* 0X1FFF7800 0x0f8f77ff 0xFFEFF8AA 0x0FDF77FF 0xFFEFF8AA
|
|
* 0X1FFF7808 0x0000FFFF 0xFFFFFFFF 0x0000FFFF 0xFFFFFFFF
|
|
* 0X1FFF7810 0x8000FFFF 0 0x8000FFFF 0
|
|
* 0X1FFF7818 0x00FF00FF 0x000000ff 0x00FF00FF 0x000000ff
|
|
* 0X1FFF7820 0x00FF00FF 0x000000ff 0x00FF00FF 0x000000ff
|
|
* 0X1FFFF808 0 0 0x8000FFFF 0xffffffff
|
|
* 0X1FFFF810 0 0 0x8000FFFF 0
|
|
* 0X1FFFF818 0 0 0x00FF00FF 0
|
|
* 0X1FFFF820 0 0 0x00FF00FF 0x000000ff
|
|
*/
|
|
|
|
static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
|
|
{
|
|
uint32_t val;
|
|
uint32_t values[9] = { 0xFFEFF8AA, 0xFFFFFFFF, 0, 0x000000ff,
|
|
0x000000ff, 0xffffffff, 0, 0xff, 0x000000ff};
|
|
int len;
|
|
bool res = false;
|
|
|
|
const uint8_t *i2offset = l4_i2offset;
|
|
if (t->idcode == 0x435) {/* L43x */
|
|
len = 5;
|
|
} else if (t->idcode == ID_STM32G07) {/* G07x */
|
|
i2offset = g0_i2offset;
|
|
len = 7;
|
|
} else {
|
|
len = 9;
|
|
}
|
|
if ((argc == 2) && !strcmp(argv[1], "erase")) {
|
|
res = stm32l4_option_write(t, values, len, i2offset);
|
|
} else if ((argc > 2) && !strcmp(argv[1], "write")) {
|
|
int i;
|
|
for (i = 2; i < argc; i++)
|
|
values[i - 2] = strtoul(argv[i], NULL, 0);
|
|
for (i = i - 2; i < len; i++) {
|
|
uint32_t addr = FPEC_BASE + i2offset[i];
|
|
values[i] = target_mem_read32(t, addr);
|
|
}
|
|
if ((values[0] & 0xff) == 0xCC) {
|
|
values[0]++;
|
|
tc_printf(t, "Changing Level 2 request to Level 1!");
|
|
}
|
|
res = stm32l4_option_write(t, values, len, i2offset);
|
|
} else {
|
|
tc_printf(t, "usage: monitor option erase\n");
|
|
tc_printf(t, "usage: monitor option write <value> ...\n");
|
|
}
|
|
if (res) {
|
|
tc_printf(t, "Writing options failed!\n");
|
|
return false;
|
|
}
|
|
for (int i = 0; i < len; i ++) {
|
|
uint32_t addr = FPEC_BASE + i2offset[i];
|
|
val = target_mem_read32(t, FPEC_BASE + i2offset[i]);
|
|
tc_printf(t, "0x%08X: 0x%08X\n", addr, val);
|
|
}
|
|
return true;
|
|
}
|