Only tested with basic tx blocking, ie, the same example code as on F2/F4, but the description of the block is almost identical.
242 lines
8.9 KiB
C
242 lines
8.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_GPIO_H
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#define LIBOPENCM3_GPIO_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* GPIO port base addresses (for convenience) */
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#define GPIOA GPIO_PORT_A_BASE
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#define GPIOB GPIO_PORT_B_BASE
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#define GPIOC GPIO_PORT_C_BASE
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#define GPIOD GPIO_PORT_D_BASE
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#define GPIOE GPIO_PORT_E_BASE
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#define GPIOH GPIO_PORT_H_BASE
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/* GPIO number definitions (for convenience) */
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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#define GPIO3 (1 << 3)
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#define GPIO4 (1 << 4)
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#define GPIO5 (1 << 5)
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO8 (1 << 8)
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#define GPIO9 (1 << 9)
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#define GPIO10 (1 << 10)
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#define GPIO11 (1 << 11)
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#define GPIO12 (1 << 12)
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#define GPIO13 (1 << 13)
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#define GPIO14 (1 << 14)
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#define GPIO15 (1 << 15)
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#define GPIO_ALL 0xffff
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/* --- GPIO registers ------------------------------------------------------ */
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/* Port mode register (GPIOx_MODER) */
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#define GPIO_MODER(port) MMIO32(port + 0x00)
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#define GPIOA_MODER GPIO_MODER(GPIOA)
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#define GPIOB_MODER GPIO_MODER(GPIOB)
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#define GPIOC_MODER GPIO_MODER(GPIOC)
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#define GPIOD_MODER GPIO_MODER(GPIOD)
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#define GPIOE_MODER GPIO_MODER(GPIOE)
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#define GPIOH_MODER GPIO_MODER(GPIOH)
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/* Port output type register (GPIOx_OTYPER) */
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#define GPIO_OTYPER(port) MMIO32(port + 0x04)
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#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
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#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
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#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
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#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
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#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
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#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
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/* Port output speed register (GPIOx_OSPEEDR) */
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#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
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#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
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#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
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#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
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#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
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#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
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#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
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/* Port pull-up/pull-down register (GPIOx_PUPDR) */
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#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
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#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
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#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
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#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
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#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
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#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
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#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
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/* Port input data register (GPIOx_IDR) */
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#define GPIO_IDR(port) MMIO32(port + 0x10)
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#define GPIOA_IDR GPIO_IDR(GPIOA)
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#define GPIOB_IDR GPIO_IDR(GPIOB)
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#define GPIOC_IDR GPIO_IDR(GPIOC)
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#define GPIOD_IDR GPIO_IDR(GPIOD)
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#define GPIOE_IDR GPIO_IDR(GPIOE)
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#define GPIOH_IDR GPIO_IDR(GPIOH)
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/* Port output data register (GPIOx_ODR) */
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#define GPIO_ODR(port) MMIO32(port + 0x14)
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#define GPIOA_ODR GPIO_ODR(GPIOA)
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#define GPIOB_ODR GPIO_ODR(GPIOB)
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#define GPIOC_ODR GPIO_ODR(GPIOC)
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#define GPIOD_ODR GPIO_ODR(GPIOD)
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#define GPIOE_ODR GPIO_ODR(GPIOE)
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#define GPIOH_ODR GPIO_ODR(GPIOH)
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/* Port bit set/reset register (GPIOx_BSRR) */
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#define GPIO_BSRR(port) MMIO32(port + 0x18)
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#define GPIOA_BSRR GPIO_BSRR(GPIOA)
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#define GPIOB_BSRR GPIO_BSRR(GPIOB)
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#define GPIOC_BSRR GPIO_BSRR(GPIOC)
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#define GPIOD_BSRR GPIO_BSRR(GPIOD)
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#define GPIOE_BSRR GPIO_BSRR(GPIOE)
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#define GPIOH_BSRR GPIO_BSRR(GPIOH)
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/* Port configuration lock register (GPIOx_LCKR) */
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#define GPIO_LCKR(port) MMIO32(port + 0x1C)
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#define GPIOA_LCKR GPIO_LCKR(GPIOA)
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#define GPIOB_LCKR GPIO_LCKR(GPIOB)
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#define GPIOC_LCKR GPIO_LCKR(GPIOC)
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#define GPIOD_LCKR GPIO_LCKR(GPIOD)
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#define GPIOE_LCKR GPIO_LCKR(GPIOE)
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#define GPIOH_LCKR GPIO_LCKR(GPIOH)
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/* Alternate function low register (GPIOx_AFRL) */
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#define GPIO_AFRL(port) MMIO32(port + 0x20)
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#define GPIOA_AFRL GPIO_AFRL(GPIOA)
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#define GPIOB_AFRL GPIO_AFRL(GPIOB)
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#define GPIOC_AFRL GPIO_AFRL(GPIOC)
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#define GPIOD_AFRL GPIO_AFRL(GPIOD)
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#define GPIOE_AFRL GPIO_AFRL(GPIOE)
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#define GPIOH_AFRL GPIO_AFRL(GPIOH)
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/* Alternate function high register (GPIOx_AFRH) */
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#define GPIO_AFRH(port) MMIO32(port + 0x24)
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#define GPIOA_AFRH GPIO_AFRH(GPIOA)
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#define GPIOB_AFRH GPIO_AFRH(GPIOB)
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#define GPIOC_AFRH GPIO_AFRH(GPIOC)
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#define GPIOD_AFRH GPIO_AFRH(GPIOD)
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#define GPIOE_AFRH GPIO_AFRH(GPIOE)
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#define GPIOH_AFRH GPIO_AFRH(GPIOH)
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/* --- GPIOx_MODER values-------------------------------------------- */
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#define GPIO_MODE(n, mode) (mode << (2 * (n)))
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#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
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#define GPIO_MODE_INPUT 0x00 /* Default */
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#define GPIO_MODE_OUTPUT 0x01
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#define GPIO_MODE_AF 0x02
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#define GPIO_MODE_ANALOG 0x03
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/* --- GPIOx_OTYPER values -------------------------------------------- */
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/* Output type (OTx values) */
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#define GPIO_OTYPE_PP 0x0
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#define GPIO_OTYPE_OD 0x1
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/* Output speed values */
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#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
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#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
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#define GPIO_OSPEED_400KHZ 0x0
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#define GPIO_OSPEED_2MHZ 0x1
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#define GPIO_OSPEED_10MHZ 0x2
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#define GPIO_OSPEED_40MHZ 0x3
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/* --- GPIOx_PUPDR values ------------------------------------------- */
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#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
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#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
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#define GPIO_PUPD_NONE 0x0
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#define GPIO_PUPD_PULLUP 0x1
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#define GPIO_PUPD_PULLDOWN 0x2
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/* --- GPIO_IDR values ----------------------------------------------------- */
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/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
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/* --- GPIO_ODR values ----------------------------------------------------- */
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/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
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/* --- GPIO_BSRR values ---------------------------------------------------- */
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/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
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/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
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/* --- GPIO_LCKR values ---------------------------------------------------- */
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#define GPIO_LCKK (1 << 16)
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/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
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/* --- GPIOx_AFRL/H values ------------------------------------------------- */
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/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
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/* See datasheet table 5, page 35 for the definitions */
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#define GPIO_AFR(n, af) (af << ((n) * 4))
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#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
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#define GPIO_AF0 0x0
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#define GPIO_AF1 0x1
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#define GPIO_AF2 0x2
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#define GPIO_AF3 0x3
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#define GPIO_AF4 0x4
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#define GPIO_AF5 0x5
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#define GPIO_AF6 0x6
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#define GPIO_AF7 0x7
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#define GPIO_AF8 0x8
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#define GPIO_AF9 0x9
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#define GPIO_AF10 0xa
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#define GPIO_AF11 0xb
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#define GPIO_AF12 0xc
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#define GPIO_AF13 0xd
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#define GPIO_AF14 0xe
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#define GPIO_AF15 0xf
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/* --- Function prototypes ------------------------------------------------- */
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/*
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* L1, like F2 and F4, has the "new" GPIO peripheral, so use that style
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* TODO: this should all really be moved to a "common" gpio header
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*/
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void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
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void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
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void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
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/* F1 compatible api */
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void gpio_set(u32 gpioport, u16 gpios);
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void gpio_clear(u32 gpioport, u16 gpios);
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u16 gpio_get(u32 gpioport, u16 gpios);
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void gpio_toggle(u32 gpioport, u16 gpios);
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u16 gpio_port_read(u32 gpioport);
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void gpio_port_write(u32 gpioport, u16 data);
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void gpio_port_config_lock(u32 gpioport, u16 gpios);
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#endif
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