c72f3d588a
All the macro arguments that are user supplied, or potentially, wrap properly in () as good practice. Probably missed one or two, and a lot of them are possibly unnecessary, but it's straightforward to just do it always. Fixes github issue #321
114 lines
3.9 KiB
C
114 lines
3.9 KiB
C
/** @defgroup adc_defines ADC Defines
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@brief <b>Defined Constants and Types for the LPC43xx A/D Converter</b>
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@ingroup LPC43xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
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@date 10 March 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_ADC_H
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#define LPC43XX_ADC_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* ADC port base addresses (for convenience) */
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#define ADC0 ADC0_BASE
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#define ADC1 ADC1_BASE
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/* --- ADC registers ------------------------------------------------------- */
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/* A/D Control Register */
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#define ADC_CR(port) MMIO32((port) + 0x000)
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#define ADC0_CR ADC_CR(ADC0)
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#define ADC1_CR ADC_CR(ADC1)
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/* A/D Global Data Register */
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#define ADC_GDR(port) MMIO32((port) + 0x004)
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#define ADC0_GDR ADC_GDR(ADC0)
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#define ADC1_GDR ADC_GDR(ADC1)
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/* A/D Interrupt Enable Register */
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#define ADC_INTEN(port) MMIO32((port) + 0x00C)
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#define ADC0_INTEN ADC_INTEN(ADC0)
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#define ADC1_INTEN ADC_INTEN(ADC1)
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/* A/D Channel 0 Data Register */
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#define ADC_DR0(port) MMIO32((port) + 0x010)
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#define ADC0_DR0 ADC_DR0(ADC0)
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#define ADC1_DR0 ADC_DR0(ADC1)
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/* A/D Channel 1 Data Register */
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#define ADC_DR1(port) MMIO32((port) + 0x014)
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#define ADC0_DR1 ADC_DR1(ADC0)
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#define ADC1_DR1 ADC_DR1(ADC1)
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/* A/D Channel 2 Data Register */
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#define ADC_DR2(port) MMIO32((port) + 0x018)
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#define ADC0_DR2 ADC_DR2(ADC0)
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#define ADC1_DR2 ADC_DR2(ADC1)
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/* A/D Channel 3 Data Register */
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#define ADC_DR3(port) MMIO32((port) + 0x01C)
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#define ADC0_DR3 ADC_DR3(ADC0)
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#define ADC1_DR3 ADC_DR3(ADC1)
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/* A/D Channel 4 Data Register */
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#define ADC_DR4(port) MMIO32((port) + 0x020)
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#define ADC0_DR4 ADC_DR4(ADC0)
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#define ADC1_DR4 ADC_DR4(ADC1)
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/* A/D Channel 5 Data Register */
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#define ADC_DR5(port) MMIO32((port) + 0x024)
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#define ADC0_DR5 ADC_DR5(ADC0)
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#define ADC1_DR5 ADC_DR5(ADC1)
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/* A/D Channel 6 Data Register */
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#define ADC_DR6(port) MMIO32((port) + 0x028)
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#define ADC0_DR6 ADC_DR6(ADC0)
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#define ADC1_DR6 ADC_DR6(ADC1)
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/* A/D Channel 7 Data Register */
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#define ADC_DR7(port) MMIO32((port) + 0x02C)
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#define ADC0_DR7 ADC_DR7(ADC0)
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#define ADC1_DR7 ADC_DR7(ADC1)
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/* A/D Status Register */
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#define ADC_STAT(port) MMIO32((port) + 0x030)
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#define ADC0_STAT ADC_STAT(ADC0)
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#define ADC1_STAT ADC_STAT(ADC1)
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/**@}*/
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#endif
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