c72f3d588a
All the macro arguments that are user supplied, or potentially, wrap properly in () as good practice. Probably missed one or two, and a lot of them are possibly unnecessary, but it's straightforward to just do it always. Fixes github issue #321
210 lines
5.9 KiB
C
210 lines
5.9 KiB
C
/** @defgroup ssp_defines Synchronous Serial Port
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@brief <b>Defined Constants and Types for the LPC43xx Synchronous Serial
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Port</b>
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@ingroup LPC43xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
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@date 10 March 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_SSP_H
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#define LPC43XX_SSP_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* SSP port base addresses (for convenience) */
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#define SSP0 SSP0_BASE
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#define SSP1 SSP1_BASE
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/* --- SSP registers ------------------------------------------------------- */
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/* Control Register 0 */
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#define SSP_CR0(port) MMIO32((port) + 0x000)
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#define SSP0_CR0 SSP_CR0(SSP0)
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#define SSP1_CR0 SSP_CR0(SSP1)
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/* Control Register 1 */
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#define SSP_CR1(port) MMIO32((port) + 0x004)
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#define SSP0_CR1 SSP_CR1(SSP0)
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#define SSP1_CR1 SSP_CR1(SSP1)
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/* Data Register */
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#define SSP_DR(port) MMIO32((port) + 0x008)
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#define SSP0_DR SSP_DR(SSP0)
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#define SSP1_DR SSP_DR(SSP1)
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/* Status Register */
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#define SSP_SR(port) MMIO32((port) + 0x00C)
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#define SSP0_SR SSP_SR(SSP0)
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#define SSP1_SR SSP_SR(SSP1)
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#define SSP_SR_TFE BIT0
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#define SSP_SR_TNF BIT1
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#define SSP_SR_RNE BIT2
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#define SSP_SR_RFF BIT3
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#define SSP_SR_BSY BIT4
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/* Clock Prescale Register */
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#define SSP_CPSR(port) MMIO32((port) + 0x010)
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#define SSP0_CPSR SSP_CPSR(SSP0)
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#define SSP1_CPSR SSP_CPSR(SSP1)
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/* Interrupt Mask Set and Clear Register */
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#define SSP_IMSC(port) MMIO32((port) + 0x014)
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#define SSP0_IMSC SSP_IMSC(SSP0)
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#define SSP1_IMSC SSP_IMSC(SSP1)
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/* Raw Interrupt Status Register */
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#define SSP_RIS(port) MMIO32((port) + 0x018)
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#define SSP0_RIS SSP_RIS(SSP0)
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#define SSP1_RIS SSP_RIS(SSP1)
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/* Masked Interrupt Status Register */
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#define SSP_MIS(port) MMIO32((port) + 0x01C)
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#define SSP0_MIS SSP_MIS(SSP0)
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#define SSP1_MIS SSP_MIS(SSP1)
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/* SSPICR Interrupt Clear Register */
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#define SSP_ICR(port) MMIO32((port) + 0x020)
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#define SSP0_ICR SSP_ICR(SSP0)
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#define SSP1_ICR SSP_ICR(SSP1)
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/* SSP1 DMA control register */
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#define SSP_DMACR(port) MMIO32((port) + 0x024)
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#define SSP0_DMACR SSP_DMACR(SSP0)
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#define SSP1_DMACR SSP_DMACR(SSP1)
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/* RXDMAE: Receive DMA enable */
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#define SSP_DMACR_RXDMAE 0x1
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/* RXDMAE: Transmit DMA enable */
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#define SSP_DMACR_TXDMAE 0x2
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typedef enum {
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SSP0_NUM = 0x0,
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SSP1_NUM = 0x1
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} ssp_num_t;
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/*
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* SSP Control Register 0
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*/
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/* SSP Data Size Bits 0 to 3 */
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typedef enum {
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SSP_DATA_4BITS = 0x3,
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SSP_DATA_5BITS = 0x4,
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SSP_DATA_6BITS = 0x5,
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SSP_DATA_7BITS = 0x6,
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SSP_DATA_8BITS = 0x7,
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SSP_DATA_9BITS = 0x8,
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SSP_DATA_10BITS = 0x9,
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SSP_DATA_11BITS = 0xA,
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SSP_DATA_12BITS = 0xB,
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SSP_DATA_13BITS = 0xC,
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SSP_DATA_14BITS = 0xD,
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SSP_DATA_15BITS = 0xE,
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SSP_DATA_16BITS = 0xF
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} ssp_datasize_t;
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/* SSP Frame Format/Type Bits 4 & 5 */
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typedef enum {
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SSP_FRAME_SPI = 0x00,
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SSP_FRAME_TI = BIT4,
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SSP_FRAM_MICROWIRE = BIT5
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} ssp_frame_format_t;
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/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */
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typedef enum {
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SSP_CPOL_0_CPHA_0 = 0x0,
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SSP_CPOL_1_CPHA_0 = BIT6,
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SSP_CPOL_0_CPHA_1 = BIT7,
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SSP_CPOL_1_CPHA_1 = (BIT6|BIT7)
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} ssp_cpol_cpha_t;
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/*
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* SSP Control Register 1
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*/
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/* SSP Mode Bit0 */
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typedef enum {
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SSP_MODE_NORMAL = 0x0,
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SSP_MODE_LOOPBACK = BIT0
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} ssp_mode_t;
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/* SSP Enable Bit1 */
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#define SSP_ENABLE BIT1
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/* SSP Master/Slave Mode Bit2 */
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typedef enum {
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SSP_MASTER = 0x0,
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SSP_SLAVE = BIT2
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} ssp_master_slave_t;
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/*
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* SSP Slave Output Disable Bit3
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* Slave Output Disable. This bit is relevant only in slave mode
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* (MS = 1). If it is 1, this blocks this SSP controller from driving the
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* transmit data line (MISO).
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*/
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typedef enum {
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SSP_SLAVE_OUT_ENABLE = 0x0,
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SSP_SLAVE_OUT_DISABLE = BIT3
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} ssp_slave_option_t; /* This option is relevant only in slave mode */
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BEGIN_DECLS
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void ssp_disable(ssp_num_t ssp_num);
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/*
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* SSP Init
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* clk_prescale shall be in range 2 to 254 (even number only).
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* Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale,
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* SCR=serial_clock_rate
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*/
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void ssp_init(ssp_num_t ssp_num,
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ssp_datasize_t data_size,
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ssp_frame_format_t frame_format,
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ssp_cpol_cpha_t cpol_cpha_format,
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uint8_t serial_clock_rate,
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uint8_t clk_prescale,
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ssp_mode_t mode,
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ssp_master_slave_t master_slave,
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ssp_slave_option_t slave_option);
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uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data);
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END_DECLS
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/**@}*/
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#endif
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