3c4ee6f4c0
Updates the main memory map and the makefile. Adds the SWM050 to devices.data, so that a linker script can be automatically generated. Reviewed-by: Karl Palsson <karlp@tweak.net.au>
51 lines
1.8 KiB
C
51 lines
1.8 KiB
C
/** @defgroup sysctl_defines SYSCTL Defines
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*
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* @brief <b>Defined Constants and Types for the SWM050 SYSCTL Registers</b>
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*
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* @ingroup SWM050_defines
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Caleb Szalacinski <contact@skiboy.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_SYSCTL_H
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#define LIBOPENCM3_SYSCTL_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/swm050/memorymap.h>
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/** @defgroup sysctl_register SYSCTL Registers
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* @note System configuration registers
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* @{*/
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/** Clock dividers for TIMERSE and SCLK */
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#define SYSCTL_SYS_CFG_0 MMIO32(SYSCTL_BASE + 0x0)
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/** TIMERSE0, TIMERSE1, and WDT enable */
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#define SYSCTL_SYS_CFG_1 MMIO32(SYSCTL_BASE + 0x4)
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/** SCLK multiplier (18Mhz and 36Mhz) */
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#define SYSCTL_SYS_DBLF MMIO32(SYSCTL_BASE + 0x8)
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/** MOS Disconnect (Synwit says that this subregister is unused), Sleep Mode,
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and Internal Oscillator Disconnect. Oscillator Disconnect should probably
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not be used on the SWM050, because it has no external oscillator support */
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#define SYSCTL_SYS_CFG_2 MMIO32(SYSCTL_BASE + 0xC)
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/*@}*/
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#endif
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/**@}*/
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