3c6e9fd56d
So that the navigation pane works correctly in browsers. Some additional doc fixes put in where found (but many more still to go). Added some dummy .c and .h files to bring the associated docs into line. makefile changed to allow 'make html' as well as 'make doc' (the latter only does html anyway).
599 lines
20 KiB
C
599 lines
20 KiB
C
/** @defgroup rcc_defines RCC Defines
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*
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* @brief <b>Defined Constants and Types for the STM32F3xx Reset and Clock
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* Control</b>
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*
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* @ingroup STM32F3xx_defines
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*
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* @author @htmlonly © @endhtmlonly 2009
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* Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
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* @author @htmlonly © @endhtmlonly 2009
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* Uwe Hermann <uwe@hermann-uwe.de>
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* @author @htmlonly © @endhtmlonly 2011
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* Fergus Noble <fergusnoble@gmail.com>
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* @author @htmlonly © @endhtmlonly 2011
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* Stephen Caudle <scaudle@doceme.com>
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* @author @htmlonly © @endhtmlonly 2013
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* Fernando Cortes <fernando.corcam@gmail.com>
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* @author @htmlonly © @endhtmlonly 2013
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* Guillermo Rivera <memogrg@gmail.com>
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*
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* @version 1.0.0
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*
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* @date 11 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
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* Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3)
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* Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3)
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
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#define RCC_CIR MMIO32(RCC_BASE + 0x08)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0C)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1C)
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#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
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#define RCC_CSR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)
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#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2C)
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#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30)
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/* --- RCC_CR values ------------------------------------------------------- */
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_CSSON (1 << 19)
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#define RCC_CR_HSEBYP (1 << 18)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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/* HSICAL: [15:8] */
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/* HSITRIM: [7:3] */
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
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/* --- RCC_CFGR values ----------------------------------------------------- */
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#define RCC_CFGR_MCOF (1 << 28)
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#define RCC_CFGR_I2SSRC (1 << 23)
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#define RCC_CFGR_USBPRES (1 << 22)
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#define RCC_CFGR_PLLXTPRE (1 << 17)
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#define RCC_CFGR_PLLSRC (1 << 16)
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/* MCO: Microcontroller clock output */
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#define RCC_CFGR_MCO_SHIFT 24
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#define RCC_CFGR_MCO_DISABLED 0x0
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/*Reserve RCC_CFGR_MCO 0x1*/
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#define RCC_CFGR_MCO_LSI 0x2
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#define RCC_CFGR_MCO_LSE 0x3
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#define RCC_CFGR_MCO_SYSCLK 0x4
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#define RCC_CFGR_MCO_HSI 0x5
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#define RCC_CFGR_MCO_HSE 0x6
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#define RCC_CFGR_MCO_PLL 0x7
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/* PLLSRC: PLL source values */
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#define RCC_CFGR_PLLSRC_HSI_DIV2 0
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#define RCC_CFGR_PLLSRC_HSE_PREDIV 1
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/* PLLMUL: PLL multiplication factor */
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#define RCC_CFGR_PLLMUL_SHIFT 18
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2 0x0
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3 0x1
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4 0x2
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X5 0x3
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X6 0x4
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X7 0x5
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X8 0x6
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X9 0x7
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X10 0x8
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X11 0x9
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X12 0xA
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X13 0xB
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14 0xC
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15 0xD
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#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16 0xE
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#define RCC_CFGR_PLLMUL_MASK (0xF << RCC_CFGR_PLLMUL_SHIFT)
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define RCC_CFGR_PPRE2_SHIFT 11
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/* 0XX: HCLK not divided */
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#define RCC_CFGR_PPRE2_DIV_NONE 0x0
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#define RCC_CFGR_PPRE2_DIV_2 0x4
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#define RCC_CFGR_PPRE2_DIV_4 0x5
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#define RCC_CFGR_PPRE2_DIV_8 0x6
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#define RCC_CFGR_PPRE2_DIV_16 0x7
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/* PPRE1:APB Low-speed prescaler (APB1) */
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#define RCC_CFGR_PPRE1_SHIFT 8
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/* 0XX: HCLK not divided */
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#define RCC_CFGR_PPRE1_DIV_NONE 0x0
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#define RCC_CFGR_PPRE1_DIV_2 0x4
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#define RCC_CFGR_PPRE1_DIV_4 0x5
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#define RCC_CFGR_PPRE1_DIV_8 0x6
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#define RCC_CFGR_PPRE1_DIV_16 0x7
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/* HPRE: HLCK prescaler */
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#define RCC_CFGR_HPRE_SHIFT 4
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/* 0XXX: SYSCLK not divided */
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#define RCC_CFGR_HPRE_DIV_NONE 0x0
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#define RCC_CFGR_HPRE_DIV_2 0x8
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#define RCC_CFGR_HPRE_DIV_4 0x9
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#define RCC_CFGR_HPRE_DIV_8 0xA
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#define RCC_CFGR_HPRE_DIV_16 0xB
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#define RCC_CFGR_HPRE_DIV_64 0xC
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#define RCC_CFGR_HPRE_DIV_128 0xD
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#define RCC_CFGR_HPRE_DIV_256 0xE
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#define RCC_CFGR_HPRE_DIV_512 0xF
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/* SWS: System clock switch status */
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#define RCC_CFGR_SWS_SHIFT 2
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#define RCC_CFGR_SWS_HSI 0x0
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#define RCC_CFGR_SWS_HSE 0x1
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#define RCC_CFGR_SWS_PLL 0x2
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/* SW: System clock switch */
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#define RCC_CFGR_SW_SHIFT 0
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#define RCC_CFGR_SW_HSI 0x0
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#define RCC_CFGR_SW_HSE 0x1
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#define RCC_CFGR_SW_PLL 0x2
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/* --- RCC_CIR values ------------------------------------------------------ */
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/* Clock security system interrupt clear bit */
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#define RCC_CIR_CSSC (1 << 23)
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/* OSC ready interrupt clear bits */
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#define RCC_CIR_PLLRDYC (1 << 20)
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#define RCC_CIR_HSERDYC (1 << 19)
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#define RCC_CIR_HSIRDYC (1 << 18)
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#define RCC_CIR_LSERDYC (1 << 17)
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#define RCC_CIR_LSIRDYC (1 << 16)
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/* OSC ready interrupt enable bits */
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#define RCC_CIR_PLLRDYIE (1 << 12)
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#define RCC_CIR_HSERDYIE (1 << 11)
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#define RCC_CIR_HSIRDYIE (1 << 10)
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#define RCC_CIR_LSERDYIE (1 << 9)
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#define RCC_CIR_LSIRDYIE (1 << 8)
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/* Clock security system interrupt flag bit */
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#define RCC_CIR_CSSF (1 << 7)
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/* OSC ready interrupt flag bits */
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#define RCC_CIR_PLLRDYF (1 << 4)
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#define RCC_CIR_HSERDYF (1 << 3)
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#define RCC_CIR_HSIRDYF (1 << 2)
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#define RCC_CIR_LSERDYF (1 << 1)
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#define RCC_CIR_LSIRDYF (1 << 0)
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/* --- RCC_APB2RSTR values ------------------------------------------------- */
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#define RCC_APB2RSTR_TIM17RST (1 << 18)
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#define RCC_APB2RSTR_TIM16RST (1 << 17)
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#define RCC_APB2RSTR_TIM15RST (1 << 16)
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#define RCC_APB2RSTR_USART1RST (1 << 14)
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#define RCC_APB2RSTR_TIM8RST (1 << 13)
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#define RCC_APB2RSTR_SPI1RST (1 << 12)
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#define RCC_APB2RSTR_TIM1RST (1 << 11)
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#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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#define RCC_APB1RSTR_DACRST (1 << 29)
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#define RCC_APB1RSTR_PWRRST (1 << 28)
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#define RCC_APB1RSTR_CANRST (1 << 25)
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#define RCC_APB1RSTR_USBRST (1 << 23)
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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#define RCC_APB1RSTR_I2C1RST (1 << 21)
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#define RCC_APB1RSTR_UART5RST (1 << 20)
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#define RCC_APB1RSTR_UART4RST (1 << 19)
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#define RCC_APB1RSTR_USART3RST (1 << 18)
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#define RCC_APB1RSTR_USART2RST (1 << 17)
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#define RCC_APB1RSTR_SPI3RST (1 << 15)
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#define RCC_APB1RSTR_SPI2RST (1 << 14)
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#define RCC_APB1RSTR_WWDGRST (1 << 11)
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#define RCC_APB1RSTR_TIM7RST (1 << 5)
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#define RCC_APB1RSTR_TIM6RST (1 << 4)
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#define RCC_APB1RSTR_TIM4RST (1 << 2)
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#define RCC_APB1RSTR_TIM3RST (1 << 1)
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#define RCC_APB1RSTR_TIM2RST (1 << 0)
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/* --- RCC_AHBENR values --------------------------------------------------- */
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#define RCC_AHBENR_ADC34EN (1 << 29)
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#define RCC_AHBENR_ADC12EN (1 << 28)
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#define RCC_AHBENR_TSCEN (1 << 24)
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#define RCC_AHBENR_IOPFEN (1 << 22)
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#define RCC_AHBENR_IOPEEN (1 << 21)
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#define RCC_AHBENR_IOPDEN (1 << 20)
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#define RCC_AHBENR_IOPCEN (1 << 19)
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#define RCC_AHBENR_IOPBEN (1 << 18)
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#define RCC_AHBENR_IOPAEN (1 << 17)
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#define RCC_AHBENR_CRCEN (1 << 1)
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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#define RCC_APB2ENR_TIM17EN (1 << 18)
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#define RCC_APB2ENR_TIM16EN (1 << 17)
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#define RCC_APB2ENR_TIM15EN (1 << 16)
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#define RCC_APB2ENR_USART1EN (1 << 14)
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#define RCC_APB2ENR_TIM8EN (1 << 13)
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#define RCC_APB2ENR_SPI1EN (1 << 12)
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#define RCC_APB2ENR_TIM1EN (1 << 11)
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#define RCC_APB2ENR_SYSCFGEN (1 << 0)
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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#define RCC_APB1ENR_DACEN (1 << 29)
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#define RCC_APB1ENR_PWREN (1 << 28)
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#define RCC_APB1ENR_CANEN (1 << 25)
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#define RCC_APB1ENR_USBEN (1 << 23)
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#define RCC_APB1ENR_I2C2EN (1 << 22)
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#define RCC_APB1ENR_I2C1EN (1 << 21)
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#define RCC_APB1ENR_USART2EN (1 << 17)
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#define RCC_APB1ENR_SPI3EN (1 << 15)
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#define RCC_APB1ENR_SPI2EN (1 << 14)
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#define RCC_APB1ENR_WWDGEN (1 << 11)
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#define RCC_APB1ENR_TIM7EN (1 << 5)
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#define RCC_APB1ENR_TIM6EN (1 << 4)
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#define RCC_APB1ENR_TIM4EN (1 << 2)
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#define RCC_APB1ENR_TIM3EN (1 << 1)
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#define RCC_APB1ENR_TIM2EN (1 << 0)
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/* --- RCC_BDCR values ----------------------------------------------------- */
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#define RCC_BDCR_BDRST (1 << 16)
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#define RCC_BDCR_RTCEN (1 << 15)
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/* RCC_BDCR[9:8]: RTCSEL */
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/* RCC_BDCR[4:3]: LSEDRV */
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#define RCC_BDCR_LSEBYP (1 << 2)
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#define RCC_BDCR_LSERDY (1 << 1)
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#define RCC_BDCR_LSEON (1 << 0)
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/* --- RCC_CSR values ------------------------------------------------------ */
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#define RCC_CSR_LPWRRSTF (1 << 31)
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#define RCC_CSR_WWDGRSTF (1 << 30)
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#define RCC_CSR_IWDGRSTF (1 << 29)
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#define RCC_CSR_SFTRSTF (1 << 28)
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#define RCC_CSR_PORRSTF (1 << 27)
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#define RCC_CSR_PINRSTF (1 << 26)
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#define RCC_CSR_OBLRSTF (1 << 25)
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#define RCC_CSR_RMVF (1 << 24)
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#define RCC_CSR_LSIRDY (1 << 1)
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#define RCC_CSR_LSION (1 << 0)
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/* --- RCC_AHBRSTR values -------------------------------------------------- */
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#define RCC_AHBRSTR_ADC34RST (1 << 29)
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#define RCC_AHBRSTR_ADC12RST (1 << 28)
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#define RCC_AHBRSTR_TSCRST (1 << 24)
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#define RCC_AHBRSTR_IOPFRST (1 << 22)
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#define RCC_AHBRSTR_IOPERST (1 << 21)
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#define RCC_AHBRSTR_IOPDRST (1 << 20)
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#define RCC_AHBRSTR_IOPCRST (1 << 19)
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#define RCC_AHBRSTR_IOPBRST (1 << 18)
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#define RCC_AHBRSTR_IOPARST (1 << 17)
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/* --- RCC_CFGR2 values ---------------------------------------------------- */
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/* ADC34PRES: ADC34 prescaler */
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#define RCC_CFGR2_ADC34PRES_SHIFT 9
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1 0x10
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_2 0x11
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_4 0x12
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_6 0x13
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_8 0x14
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_10 0x15
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_12 0x16
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_16 0x17
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_32 0x18
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64 0x19
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128 0x1A
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#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256 0x1B
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/* OTHERS */
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/* #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256 0x */
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/* ADC12PRES ADC prescaler */
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/* REVISAR DIRECCIONES */
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#define RCC_CFGR2_ADC12PRES_SHIFT 4
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1 0x10
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2 0x11
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_4 0x12
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_6 0x13
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_8 0x14
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_10 0x15
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_12 0x16
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_16 0x17
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_32 0x18
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64 0x19
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128 0x1A
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#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256 0x1B
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/* OTHERS */
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/* #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256 0x */
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/* PREDIV[3:0] PREDIV division factor */
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/* REVISAR DIRECCIONES */
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#define RCC_CFGR2_PREDIV_SHIFT 0
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_NONE 0x0
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_2 0x1
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_3 0x2
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_4 0x3
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_5 0x4
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_6 0x5
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_7 0x6
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_8 0x7
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_9 0x8
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_10 0x9
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_11 0xA
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_12 0xB
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_13 0xC
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_14 0xD
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_15 0xE
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#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_16 0xF
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/* --- RCC_CFGR3 values ---------------------------------------------------- */
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#define RCC_CFGR3_TIM8SW (1 << 9)
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#define RCC_CFGR3_TIM1SW (1 << 8)
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#define RCC_CFGR3_I2C2SW (1 << 5)
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#define RCC_CFGR3_I2C1SW (1 << 4)
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/* UART5SW: UART5 clock source selection */
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#define RCC_CFGR3_UART5SW_SHIFT 22
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#define RCC_CFGR3_UART5SW_PCLK 0x0
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#define RCC_CFGR3_UART5SW_SYSCLK 0x1
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#define RCC_CFGR3_UART5SW_LSE 0x2
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#define RCC_CFGR3_UART5SW_HSI 0x3
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/* UART4SW: UART4 clock source selection */
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#define RCC_CFGR3_UART4SW_SHIFT 20
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#define RCC_CFGR3_UART4SW_PCLK 0x0
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#define RCC_CFGR3_UART4SW_SYSCLK 0x1
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#define RCC_CFGR3_UART4SW_LSE 0x2
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#define RCC_CFGR3_UART4SW_HSI 0x3
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/* UART3SW: UART3 clock source selection */
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#define RCC_CFGR3_UART3SW_SHIFT 18
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#define RCC_CFGR3_UART3SW_PCLK 0x0
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#define RCC_CFGR3_UART3SW_SYSCLK 0x1
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#define RCC_CFGR3_UART3SW_LSE 0x2
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#define RCC_CFGR3_UART3SW_HSI 0x3
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/* UART2SW: UART2 clock source selection */
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#define RCC_CFGR3_UART2SW_SHIFT 16
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#define RCC_CFGR3_UART2SW_PCLK 0x0
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#define RCC_CFGR3_UART2SW_SYSCLK 0x1
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#define RCC_CFGR3_UART2SW_LSE 0x2
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#define RCC_CFGR3_UART2SW_HSI 0x3
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/* UART1SW: UART1 clock source selection */
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#define RCC_CFGR3_UART1SW_SHIFT 0
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#define RCC_CFGR3_UART1SW_PCLK 0x0
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#define RCC_CFGR3_UART1SW_SYSCLK 0x1
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#define RCC_CFGR3_UART1SW_LSE 0x2
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#define RCC_CFGR3_UART1SW_HSI 0x3
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/* --- Variable definitions ------------------------------------------------ */
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extern uint32_t rcc_ppre1_frequency;
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extern uint32_t rcc_ppre2_frequency;
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/* --- Function prototypes ------------------------------------------------- */
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enum rcc_clock {
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CLOCK_44MHZ,
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CLOCK_48MHZ,
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CLOCK_64MHZ,
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CLOCK_END
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};
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typedef struct {
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uint8_t pll;
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uint8_t pllsrc;
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uint32_t flash_config;
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uint8_t hpre;
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uint8_t ppre1;
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uint8_t ppre2;
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uint8_t power_save;
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uint32_t apb1_frequency;
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uint32_t apb2_frequency;
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} clock_scale_t;
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extern const clock_scale_t hsi_8mhz[CLOCK_END];
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enum osc {
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PLL, HSE, HSI, LSE, LSI
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};
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#define _REG_BIT(base, bit) (((base) << 5) + (bit))
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/* Availability in comment:
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* 0: F30x
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* 1: F31x
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* 7: F37x
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* 8: F38x
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*/
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enum rcc_periph_clken {
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/* AHB peripherals*/
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RCC_DMA1 = _REG_BIT(0x14, 0),/*0178*/
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RCC_DMA2 = _REG_BIT(0x14, 1),/*0178*/
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RCC_SRAM = _REG_BIT(0x14, 2),/*0178*/
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RCC_FLTIF = _REG_BIT(0x14, 4),/*0178*/
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RCC_CRC = _REG_BIT(0x14, 6),/*0178*/
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RCC_GPIOA = _REG_BIT(0x14, 17),/*0178*/
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RCC_GPIOB = _REG_BIT(0x14, 18),/*0178*/
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RCC_GPIOC = _REG_BIT(0x14, 19),/*0178*/
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RCC_GPIOD = _REG_BIT(0x14, 20),/*0178*/
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RCC_GPIOE = _REG_BIT(0x14, 21),/*0178*/
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RCC_GPIOF = _REG_BIT(0x14, 22),/*0178*/
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RCC_TSC = _REG_BIT(0x14, 24),/*0178*/
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RCC_ADC12 = _REG_BIT(0x14, 28),/*01--*/
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RCC_ADC34 = _REG_BIT(0x14, 29),/*01--*/
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/* APB2 peripherals */
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RCC_SYSCFG = _REG_BIT(0x18, 0),/*0178*/
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RCC_ADC = _REG_BIT(0x18, 9),/*--78*/
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RCC_TIM1 = _REG_BIT(0x18, 11),/*01--*/
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RCC_SPI1 = _REG_BIT(0x18, 12),/*0178*/
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RCC_TIM8 = _REG_BIT(0x18, 13),/*01--*/
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RCC_USART1 = _REG_BIT(0x18, 14),/*0178*/
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RCC_TIM15 = _REG_BIT(0x18, 16),/*0178*/
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RCC_TIM16 = _REG_BIT(0x18, 17),/*0178*/
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RCC_TIM17 = _REG_BIT(0x18, 18),/*0178*/
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RCC_TIM19 = _REG_BIT(0x18, 19),/*--78*/
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RCC_DBGMCU = _REG_BIT(0x18, 22),/*--78*/
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RCC_SDADC1 = _REG_BIT(0x18, 24),/*--78*/
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RCC_SDADC2 = _REG_BIT(0x18, 25),/*--78*/
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RCC_SDADC3 = _REG_BIT(0x18, 26),/*--78*/
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/* APB1 peripherals */
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RCC_TIM2 = _REG_BIT(0x1C, 0),/*0178*/
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RCC_TIM3 = _REG_BIT(0x1C, 1),/*0178*/
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RCC_TIM4 = _REG_BIT(0x1C, 2),/*0178*/
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RCC_TIM5 = _REG_BIT(0x1C, 3),/*--78*/
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RCC_TIM6 = _REG_BIT(0x1C, 4),/*0178*/
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RCC_TIM7 = _REG_BIT(0x1C, 5),/*0178*/
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RCC_TIM12 = _REG_BIT(0x1C, 6),/*--78*/
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RCC_TIM13 = _REG_BIT(0x1C, 7),/*--78*/
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RCC_TIM14 = _REG_BIT(0x1C, 8),/*--78*/
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RCC_TIM18 = _REG_BIT(0x1C, 9),/*--78*/
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RCC_WWDG = _REG_BIT(0x1C, 11),/*0178*/
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RCC_SPI2 = _REG_BIT(0x1C, 14),/*0178*/
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RCC_SPI3 = _REG_BIT(0x1C, 15),/*0178*/
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RCC_USART2 = _REG_BIT(0x1C, 17),/*0178*/
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RCC_USART3 = _REG_BIT(0x1C, 18),/*0178*/
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RCC_UART4 = _REG_BIT(0x1C, 19),/*01--*/
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RCC_UART5 = _REG_BIT(0x1C, 20),/*01--*/
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RCC_I2C1 = _REG_BIT(0x1C, 21),/*0178*/
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RCC_I2C2 = _REG_BIT(0x1C, 22),/*0178*/
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RCC_USB = _REG_BIT(0x1C, 23),/*0178*/
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RCC_CAN = _REG_BIT(0x1C, 25),/*0178*/
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RCC_DAC2 = _REG_BIT(0x1C, 26),/*--78*/
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RCC_PWR = _REG_BIT(0x1C, 28),/*0178*/
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RCC_DAC = _REG_BIT(0x1C, 29),/*12--*/
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RCC_DAC1 = _REG_BIT(0x1C, 29),/*--78*/
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RCC_CEC = _REG_BIT(0x1C, 29),/*--78*/
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};
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enum rcc_periph_rst {
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/* APB2 peripherals*/
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RST_SYSCFG = _REG_BIT(0x0C, 0),/*0178*/
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RST_ADC = _REG_BIT(0x0C, 9),/*--78*/
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RST_TIM1 = _REG_BIT(0x0C, 11),/*01--*/
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RST_SPI1 = _REG_BIT(0x0C, 12),/*0178*/
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RST_TIM8 = _REG_BIT(0x0C, 13),/*01--*/
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RST_USART1 = _REG_BIT(0x0C, 14),/*0178*/
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RST_TIM15 = _REG_BIT(0x0C, 16),/*0178*/
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RST_TIM16 = _REG_BIT(0x0C, 17),/*0178*/
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RST_TIM17 = _REG_BIT(0x0C, 18),/*0178*/
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RST_TIM19 = _REG_BIT(0x0C, 19),/*--78*/
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RST_SDADC1 = _REG_BIT(0x0C, 24),/*--78*/
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RST_SDADC2 = _REG_BIT(0x0C, 25),/*--78*/
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RST_SDADC3 = _REG_BIT(0x0C, 26),/*--78*/
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/* APB1 peripherals */
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RST_TIM2 = _REG_BIT(0x10, 0),/*0178*/
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RST_TIM3 = _REG_BIT(0x10, 1),/*0178*/
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RST_TIM4 = _REG_BIT(0x10, 2),/*0178*/
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RST_TIM5 = _REG_BIT(0x10, 3),/*--78*/
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RST_TIM6 = _REG_BIT(0x10, 4),/*0178*/
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RST_TIM7 = _REG_BIT(0x10, 5),/*0178*/
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RST_TIM12 = _REG_BIT(0x10, 6),/*--78*/
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RST_TIM13 = _REG_BIT(0x10, 7),/*--78*/
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RST_TIM14 = _REG_BIT(0x10, 8),/*--78*/
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RST_TIM18 = _REG_BIT(0x10, 9),/*--78*/
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RST_WWDG = _REG_BIT(0x10, 11),/*0178*/
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RST_SPI2 = _REG_BIT(0x10, 14),/*0178*/
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RST_SPI3 = _REG_BIT(0x10, 15),/*0178*/
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RST_USART2 = _REG_BIT(0x10, 17),/*0178*/
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RST_USART3 = _REG_BIT(0x10, 18),/*0178*/
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RST_UART4 = _REG_BIT(0x10, 19),/*01--*/
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RST_UART5 = _REG_BIT(0x10, 20),/*01--*/
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RST_I2C1 = _REG_BIT(0x10, 21),/*0178*/
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RST_I2C2 = _REG_BIT(0x10, 22),/*0178*/
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RST_USB = _REG_BIT(0x10, 23),/*0178*/
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RST_CAN = _REG_BIT(0x10, 25),/*0178*/
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RST_DAC2 = _REG_BIT(0x10, 26),/*--78*/
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RST_PWR = _REG_BIT(0x10, 28),/*0178*/
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RST_DAC = _REG_BIT(0x10, 29),/*01--*/
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RST_DAC1 = _REG_BIT(0x10, 29),/*--78*/
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RST_CEC = _REG_BIT(0x10, 30),/*--78*/
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/* AHB peripherals */
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RST_GPIOA = _REG_BIT(0x28, 17),/*0178*/
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RST_GPIOB = _REG_BIT(0x28, 18),/*0178*/
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RST_GPIOC = _REG_BIT(0x28, 19),/*0178*/
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RST_GPIOD = _REG_BIT(0x28, 20),/*0178*/
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RST_GPIOE = _REG_BIT(0x28, 21),/*0178*/
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RST_GPIOF = _REG_BIT(0x28, 22),/*0178*/
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RST_TSC = _REG_BIT(0x28, 24),/*0178*/
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RST_ADC12 = _REG_BIT(0x28, 28),/*01--*/
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RST_ADC34 = _REG_BIT(0x28, 29),/*01--*/
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/* BDCR[16] */
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RST_BD = _REG_BIT(0x20, 16),
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};
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#undef _REG_BIT
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#include <libopencm3/stm32/common/rcc_common_all.h>
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BEGIN_DECLS
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void rcc_osc_ready_int_clear(enum osc osc);
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void rcc_osc_ready_int_enable(enum osc osc);
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void rcc_osc_ready_int_disable(enum osc osc);
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int rcc_osc_ready_int_flag(enum osc osc);
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void rcc_css_int_clear(void);
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int rcc_css_int_flag(void);
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void rcc_wait_for_osc_ready(enum osc osc);
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void rcc_wait_for_osc_not_ready(enum osc osc);
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void rcc_wait_for_sysclk_status(enum osc osc);
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void rcc_osc_on(enum osc osc);
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void rcc_osc_off(enum osc osc);
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void rcc_css_enable(void);
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void rcc_css_disable(void);
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void rcc_osc_bypass_enable(enum osc osc);
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void rcc_osc_bypass_disable(enum osc osc);
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void rcc_set_sysclk_source(uint32_t clk);
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void rcc_set_pll_source(uint32_t pllsrc);
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void rcc_set_ppre2(uint32_t ppre2);
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void rcc_set_ppre1(uint32_t ppre1);
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void rcc_set_hpre(uint32_t hpre);
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void rcc_set_main_pll_hsi(uint32_t pll);
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uint32_t rcc_get_system_clock_source(void);
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void rcc_backupdomain_reset(void);
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void rcc_clock_setup_hsi(const clock_scale_t *clock);
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void rcc_set_i2c_clock_hsi(uint32_t i2c);
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void rcc_set_i2c_clock_sysclk(uint32_t i2c);
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uint32_t rcc_get_i2c_clocks(void);
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void rcc_usb_prescale_1_5(void);
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void rcc_usb_prescale_1(void);
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END_DECLS
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#endif
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