5b8953124e
F2 and F4 have a common section to deal with the options register (TIM2 and TIM5 only) L1 has been made common with timer_common_all as its options register has very different settings to F2/F4. Code is in the L1/timer.c L1/timer.h files Note that F3 and F05 timers should fit into this scheme, with F3 having additional features. Bundled with this is L1/pwr.h to change a documentation setting Also all the Doxyfiles have added "ENABLE_PREPROCESSING = NO" to fix a problem introduced by commit 118.
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
/** @defgroup pwr_defines PWR Defines
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@brief <b>Defined Constants and Types for the STM32L1xx Power Control</b>
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@ingroup STM32L1xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
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@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
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@date 1 July 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/pwr_common_all.h>
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/*
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* This file extends the common STM32 version with definitions only
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* applicable to the STM32L1 series of devices.
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*/
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/* --- PWR_CR values ------------------------------------------------------- */
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/* Bits [31:15]: Reserved */
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/* LPRUN: Low power run mode */
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#define PWR_CR_LPRUN (1 << 14)
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/* VOS[12:11]: Regulator voltage scaling output selection */
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#define PWR_CR_VOS_LSB 11
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/** @defgroup pwr_vos Voltage Scaling Output level selection
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@ingroup pwr_defines
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@{*/
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#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB)
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#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB)
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#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB)
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/**@}*/
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#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB)
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/* FWU: Fast wakeup */
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#define PWR_CR_FWU (1 << 10)
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/* ULP: Ultralow power mode */
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#define PWR_CR_ULP (1 << 9)
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/* LPSDSR: Low-power deepsleep/sleep/low power run */
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#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */
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/* --- PWR_CSR values ------------------------------------------------------- */
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/* Bits [31:11]: Reserved */
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/* EWUP3: Enable WKUP3 pin */
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#define PWR_CSR_EWUP3 (1 << 10)
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/* EWUP2: Enable WKUP2 pin */
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#define PWR_CSR_EWUP2 (1 << 9)
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/* EWUP1: Enable WKUP1 pin */
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#define PWR_CSR_EWUP1 PWR_CSR_EWUP
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/* REGLPF : Regulator LP flag */
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#define PWR_CSR_REGLPF (1 << 5)
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/* VOSF: Voltage Scaling select flag */
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#define PWR_CSR_VOSF (1 << 4)
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/* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */
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#define PWR_CSR_VREFINTRDYF (1 << 3)
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/* --- Function prototypes ------------------------------------------------- */
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typedef enum {
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RANGE1,
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RANGE2,
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RANGE3,
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} vos_scale_t;
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BEGIN_DECLS
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void pwr_set_vos_scale(vos_scale_t scale);
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END_DECLS
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#endif
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