216 lines
7.9 KiB
C
216 lines
7.9 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_NVIC_H
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#define LIBOPENSTM32_NVIC_H
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#include <libopenstm32/memorymap.h>
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#include <libopenstm32/common.h>
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/* --- NVIC Registers ------------------------------------------------------ */
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/* ISER: Interrupt Set Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
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/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
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/* ICER: Interrupt Clear Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
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/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
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/* ISPR: Interrupt Set Pending Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
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/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
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/* ICPR: Interrupt Clear Pending Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
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/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
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/* IABR: Interrupt Active Bit Register */
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/* Note: 8 32bit Registers */
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#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
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/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
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/* IPR: Interrupt Priority Registers */
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/* Note: 240 8bit Registers */
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#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
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/* STIR: Software Trigger Interrupt Register */
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#define NVIC_STIR MMIO32(STIR_BASE)
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/* --- SCB: Registers ------------------------------------------------------ */
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/* CPUID: CPUID base register */
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#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
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/* ICSR: Interrupt Control State Register */
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#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
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/* VTOR: Vector Table Offset Register */
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#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
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/* AIRCR: Application Interrupt and Reset Control Register */
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#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
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/* SCR: System Control Register */
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#define SCB_SCR MMIO32(SCB_BASE + 0x10)
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/* CCR: Configuration Control Register */
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#define SCB_CCR MMIO32(SCB_BASE + 0x14)
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/* SHP: System Handler Priority Registers */
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/* Note: 12 8bit registers */
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#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
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/* SHCSR: System Handler Control and State Register */
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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/* CFSR: Configurable Fault Status Registers */
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#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
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/* HFSR: Hard Fault Status Register */
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#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
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/* DFSR: Debug Fault Status Register */
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#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
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/* MMFAR: Memory Manage Fault Address Register */
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#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
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/* BFAR: Bus Fault Address Register */
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#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
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/* AFSR: Auxiliary Fault Status Register */
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#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
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/* --- SCB values ---------------------------------------------------------- */
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/* --- SCB_CPUID values ---------------------------------------------------- */
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/* Implementer[31:24]: Implementer code */
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#define SCP_CPUID_IMPLEMENTER_LSB 24
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/* Variant[23:20]: Variant number */
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#define SCP_CPUID_VARIANT_LSB 20
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/* Constant[19:16]: Reads as 0xF */
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#define SCP_CPUID_CONSTANT_LSB 16
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/* PartNo[15:4]: Part number of the processor */
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#define SCP_CPUID_PARTNO_LSB 4
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/* Revision[3:0]: Revision number */
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#define SCP_CPUID_REVISION_LSB 0
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/* --- SCB_ICSR values ----------------------------------------------------- */
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/* NMIPENDSET: NMI set-pending bit */
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#define SCB_ICSR_NMIPENDSET (1 << 31)
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/* Bits [30:29]: reserved - must be kept cleared */
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/* PENDSVSET: PendSV set-pending bit */
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#define SCB_ICSR_PENDSVSET (1 << 28)
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/* PENDSVCLR: PendSV clear-pending bit */
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#define SCB_ICSR_PENDSVCLR (1 << 27)
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/* PENDSTSET: SysTick exception set-pending bit */
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#define SCB_ICSR_PENDSTSET (1 << 26)
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/* PENDSTCLR: SysTick exception clear-pending bit */
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#define SCB_ICSR_PENDSTCLR (1 << 25)
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/* Bit 24: reserved - must be kept cleared */
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/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
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/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
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#define SCB_ICSR_ISRPENDING (1 << 22)
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/* VECTPENDING[21:12] Pending vector */
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#define SCB_ICSR_VECTPENDING_LSB 12
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/* RETOBASE: Return to base level */
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#define SCB_ICSR_RETOBASE (1 << 11)
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/* Bits [10:9]: reserved - must be kept cleared */
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/* VECTACTIVE[8:0] Active vector */
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#define SCB_ICSR_VECTACTIVE_LSB 0
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/* --- SCB_VTOR values ----------------------------------------------------- */
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/* Bits [31:30]: reserved - must be kept cleared */
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/* TBLOFF[29:9]: Vector table base offset field */
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#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
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/* --- SCB_AIRCR values ---------------------------------------------------- */
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/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
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#define SCB_AIRCR_VECTKEYSTAT_LSB 16
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/* ENDIANESS Data endianness bit */
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#define SCB_AIRCR_ENDIANESS (1 << 15)
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/* Bits [14:11]: reserved - must be kept cleared */
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/* PRIGROUP[10:8]: Interrupt priority grouping field */
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#define SCB_AIRCR_PRIGROUP_LSB 8
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#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB 0x3
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#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 0x4
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#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 0x5
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#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 0x6
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#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 0x7
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/* Bits [7:3]: reserved - must be kept cleared */
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/* SYSRESETREQ System reset request */
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#define SCB_AIRCR_SYSRESETREQ (1 << 2)
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/* VECTCLRACTIVE */
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#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
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/* VECTRESET */
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#define SCB_AIRCR_VECTRESET (1 << 0)
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/* --- SCB_SCR values ------------------------------------------------------ */
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/* Bits [31:5]: reserved - must be kept cleared */
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/* SEVEONPEND Send Event on Pending bit */
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#define SCB_SCR_SEVEONPEND (1 << 4)
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/* Bit 3: reserved - must be kept cleared */
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/* SLEEPDEEP */
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#define SCB_SCR_SLEEPDEEP (1 << 2)
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/* SLEEPONEXIT */
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#define SCB_SCR_SLEEPONEXIT (1 << 1)
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/* Bit 0: reserved - must be kept cleared */
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/* --- SCB_CCR values ------------------------------------------------------ */
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/* Bits [31:10]: reserved - must be kept cleared */
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/* STKALIGN */
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#define SCB_CCR_STKALIGN (1 << 9)
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/* BFHFNMIGN */
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#define SCB_CCR_BFHFNMIGN (1 << 8)
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/* Bits [7:5]: reserved - must be kept cleared */
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/* DIV_0_TRP */
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#define SCB_CCR_DIV_0_TRP (1 << 4)
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/* UNALIGN_TRP */
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#define SCB_CCR_UNALIGN_TRP (1 << 3)
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/* Bit 2: reserved - must be kept cleared */
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/* USERSETMPEND */
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#define SCB_CCR_USERSETMPEND (1 << 1)
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/* NONBASETHRDENA */
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#define SCB_CCR_NONBASETHRDENA (1 << 0)
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/* --- NVIC functions ------------------------------------------------------ */
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void nvic_enable_irq(u8 irqn);
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void nvic_disable_irq(u8 irqn);
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u8 nvic_get_pending_irq(u8 irqn);
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void nvic_set_pending_irq(u8 irqn);
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void nvic_clear_pending_irq(u8 irqn);
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u8 nvic_get_active_irq(u8 irqn);
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u8 nvic_get_irq_enabled(u8 irqn);
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void nvic_set_priority(u8 irqn, u8 priority);
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void nvic_generate_software_interrupt(u8 irqn);
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#endif
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