d7489ebfbd
Thanks to Thomas Otto for pointing out problems with the clock code in examples and his clock routine implementations. Based on that the most common clock combination routines were added to the library and all routines in examples setting up the clock replaced with calls to that functions.
405 lines
12 KiB
C
405 lines
12 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_RCC_H
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#define LIBOPENSTM32_RCC_H
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#include <libopenstm32/memorymap.h>
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#include <libopenstm32/common.h>
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/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */
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/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
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#define RCC_CIR MMIO32(RCC_BASE + 0x08)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
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#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
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#define RCC_CSR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */
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#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */
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/* --- RCC_CR values ------------------------------------------------------- */
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#define PLL3RDY (1 << 29) /* (**) */
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#define PLL3ON (1 << 28) /* (**) */
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#define PLL2RDY (1 << 27) /* (**) */
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#define PLL2ON (1 << 26) /* (**) */
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#define PLLRDY (1 << 25)
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#define PLLON (1 << 24)
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#define CSSON (1 << 19)
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#define HSEBYP (1 << 18)
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#define HSERDY (1 << 17)
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#define HSEON (1 << 16)
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/* HSICAL: [15:8] */
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/* HSITRIM: [7:3] */
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#define HSIRDY (1 << 1)
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#define HSION (1 << 0)
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/* --- RCC_CFGR values ----------------------------------------------------- */
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/* MCO: Microcontroller clock output */
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#define MCO_NOCLK 0x0
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#define MCO_SYSCLK 0x4
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#define MCO_HSICLK 0x5
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#define MCO_HSECLK 0x6
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#define MCO_PLLCLK_DIV2 0x7
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#define MCO_PLL2CLK 0x8 /* (**) */
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#define MCO_PLL3CLK_DIV2 0x9 /* (**) */
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#define MCO_XT1 0xa /* (**) */
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#define MCO_PLL3 0xb /* (**) */
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/* USBPRE: USB prescaler (RCC_CFGR[22]) */
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#define USBPRE_PLL_CLK_DIV1_5 0x0
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#define USBPRE_PLL_CLK_NODIV 0x1
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/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
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#define USBPRE_PLL_VCO_CLK_DIV3 0x0
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#define USBPRE_PLL_VCO_CLK_DIV2 0x1
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/* PLLMUL: PLL multiplication factor */
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#define PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */
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#define PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */
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#define PLLMUL_PLL_CLK_MUL4 0x2
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#define PLLMUL_PLL_CLK_MUL5 0x3
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#define PLLMUL_PLL_CLK_MUL6 0x4
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#define PLLMUL_PLL_CLK_MUL7 0x5
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#define PLLMUL_PLL_CLK_MUL8 0x6
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#define PLLMUL_PLL_CLK_MUL9 0x7
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#define PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */
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#define PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */
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#define PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */
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#define PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */
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#define PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */
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#define PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */
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#define PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
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#define PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
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// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
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/* TODO: conn. line differs. */
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/* PLLXTPRE: HSE divider for PLL entry */
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#define PLLXTPRE_HSE_CLK 0x0
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#define PLLXTPRE_HSE_CLK_DIV2 0x1
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/* PLLSRC: PLL entry clock source */
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#define PLLSRC_HSI_CLK_DIV2 0x0
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#define PLLSRC_HSE_CLK 0x1
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#define PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */
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/* ADCPRE: ADC prescaler */
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/* TODO: Datasheet says "PLCK2". Typo? Should be "PCLK2"? */
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#define ADCPRE_PLCK2_DIV2 0x0
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#define ADCPRE_PLCK2_DIV4 0x1
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#define ADCPRE_PLCK2_DIV6 0x2
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#define ADCPRE_PLCK2_DIV8 0x3
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define PPRE2_HCLK_NODIV 0x0
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#define PPRE2_HCLK_DIV2 0x4
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#define PPRE2_HCLK_DIV4 0x5
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#define PPRE2_HCLK_DIV8 0x6
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#define PPRE2_HCLK_DIV16 0x7
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/* PPRE1: APB low-speed prescaler (APB1) */
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#define PPRE1_HCLK_NODIV 0x0
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#define PPRE1_HCLK_DIV2 0x4
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#define PPRE1_HCLK_DIV4 0x5
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#define PPRE1_HCLK_DIV8 0x6
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#define PPRE1_HCLK_DIV16 0x7
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/* HPRE: AHB prescaler */
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#define HPRE_SYSCLK_NODIV 0x0
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#define HPRE_SYSCLK_DIV2 0x8
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#define HPRE_SYSCLK_DIV4 0x9
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#define HPRE_SYSCLK_DIV8 0xa
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#define HPRE_SYSCLK_DIV16 0xb
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#define HPRE_SYSCLK_DIV64 0xc
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#define HPRE_SYSCLK_DIV128 0xd
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#define HPRE_SYSCLK_DIV256 0xe
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#define HPRE_SYSCLK_DIV512 0xf
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/* SWS: System clock switch status */
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#define SWS_SYSCLKSEL_HSICLK 0x0
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#define SWS_SYSCLKSEL_HSECLK 0x1
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#define SWS_SYSCLKSEL_PLLCLK 0x2
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/* SW: System clock switch */
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#define SW_SYSCLKSEL_HSICLK 0x0
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#define SW_SYSCLKSEL_HSECLK 0x1
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#define SW_SYSCLKSEL_PLLCLK 0x2
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/* --- RCC_CIR values ------------------------------------------------------ */
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/* Clock security system interrupt clear bit */
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#define CSSC (1 << 23)
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/* OSC ready interrupt clear bits */
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#define PLL3RDYC (1 << 22) /* (**) */
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#define PLL2RDYC (1 << 21) /* (**) */
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#define PLLRDYC (1 << 20)
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#define HSERDYC (1 << 19)
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#define HSIRDYC (1 << 18)
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#define LSERDYC (1 << 17)
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#define LSIRDYC (1 << 16)
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/* OSC ready interrupt enable bits */
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#define PLL3RDYIE (1 << 14) /* (**) */
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#define PLL2RDYIE (1 << 13) /* (**) */
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#define PLLRDYIE (1 << 12)
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#define HSERDYIE (1 << 11)
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#define HSIRDYIE (1 << 10)
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#define LSERDYIE (1 << 9)
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#define LSIRDYIE (1 << 8)
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/* Clock security system interrupt flag bit */
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#define CSSF (1 << 7)
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/* OSC ready interrupt flag bits */
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#define PLL3RDYF (1 << 6) /* (**) */
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#define PLL2RDYF (1 << 5) /* (**) */
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#define PLLRDYF (1 << 4)
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#define HSERDYF (1 << 3)
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#define HSIRDYF (1 << 2)
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#define LSERDYF (1 << 1)
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#define LSIRDYF (1 << 0)
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/* --- RCC_APB2RSTR values ------------------------------------------------- */
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#define ADC3RST (1 << 15) /* (XX) */
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#define USART1RST (1 << 14)
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#define TIM8RST (1 << 13) /* (XX) */
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#define SPI1RST (1 << 12)
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#define TIM1RST (1 << 11)
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#define ADC2RST (1 << 10)
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#define ADC1RST (1 << 9)
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#define IOPGRST (1 << 8) /* (XX) */
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#define IOPFRST (1 << 7) /* (XX) */
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#define IOPERST (1 << 6)
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#define IOPDRST (1 << 5)
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#define IOPCRST (1 << 4)
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#define IOPBRST (1 << 3)
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#define IOPARST (1 << 2)
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#define AFIORST (1 << 0)
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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#define DACRST (1 << 29)
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#define PWRRST (1 << 28)
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#define BKPRST (1 << 27)
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#define CAN2RST (1 << 26) /* (**) */
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#define CAN1RST (1 << 25) /* (**) */
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#define CANRST (1 << 25) /* (XX) Alias for CAN1RST */
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#define USBRST (1 << 23) /* (XX) */
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#define I2C2RST (1 << 22)
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#define I2C1RST (1 << 21)
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#define USART5RST (1 << 20)
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#define USART4RST (1 << 19)
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#define USART3RST (1 << 18)
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#define USART2RST (1 << 17)
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#define SPI3RST (1 << 15)
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#define SPI2RST (1 << 14)
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#define WWDGRST (1 << 11)
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#define TIM7RST (1 << 5)
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#define TIM6RST (1 << 4)
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#define TIM5RST (1 << 3)
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#define TIM4RST (1 << 2)
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#define TIM3RST (1 << 1)
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#define TIM2RST (1 << 0)
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/* --- RCC_AHBENR values --------------------------------------------------- */
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#define SDIOEN (1 << 10)
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#define FSMCEN (1 << 8)
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#define CRCEN (1 << 6)
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#define FLITFEN (1 << 4)
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#define SRAMEN (1 << 2)
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#define DMA2EN (1 << 1)
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#define DMA1EN (1 << 0)
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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#define ADC3EN (1 << 15) /* (XX) */
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#define USART1EN (1 << 14)
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#define TIM8EN (1 << 13) /* (XX) */
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#define SPI1EN (1 << 12)
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#define TIM1EN (1 << 11)
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#define ADC2EN (1 << 10)
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#define ADC1EN (1 << 9)
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#define IOPGEN (1 << 8) /* (XX) */
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#define IOPFEN (1 << 7) /* (XX) */
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#define IOPEEN (1 << 6)
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#define IOPDEN (1 << 5)
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#define IOPCEN (1 << 4)
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#define IOPBEN (1 << 3)
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#define IOPAEN (1 << 2)
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#define AFIOEN (1 << 0)
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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#define DACEN (1 << 29)
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#define PWREN (1 << 28)
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#define BKPEN (1 << 27)
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#define CAN2EN (1 << 26) /* (**) */
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#define CAN1EN (1 << 25) /* (**) */
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#define CANEN (1 << 25) /* (XX) Alias for CAN1EN */
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#define USBEN (1 << 23) /* (XX) */
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#define I2C2EN (1 << 22)
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#define I2C1EN (1 << 21)
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#define USART5EN (1 << 20)
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#define USART4EN (1 << 19)
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#define USART3EN (1 << 18)
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#define USART2EN (1 << 17)
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#define SPI3EN (1 << 15)
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#define SPI2EN (1 << 14)
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#define WWDGEN (1 << 11)
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#define TIM7EN (1 << 5)
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#define TIM6EN (1 << 4)
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#define TIM5EN (1 << 3)
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#define TIM4EN (1 << 2)
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#define TIM3EN (1 << 1)
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#define TIM2EN (1 << 0)
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/* --- RCC_BDCR values ----------------------------------------------------- */
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#define BDRST (1 << 16)
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#define RTCEN (1 << 15)
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/* RCC_BDCR[9:8]: RTCSEL */
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#define LSEBYP (1 << 2)
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#define LSERDY (1 << 1)
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#define LSEON (1 << 0)
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/* --- RCC_CSR values ------------------------------------------------------ */
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#define LPWRRSTF (1 << 31)
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#define WWDGRSTF (1 << 30)
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#define IWDGRSTF (1 << 29)
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#define SFTRSTF (1 << 28)
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#define PORRSTF (1 << 27)
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#define PINRSTF (1 << 26)
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#define RMVF (1 << 24)
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#define LSIRDY (1 << 1)
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#define LSION (1 << 0)
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/* --- RCC_AHBRSTR values -------------------------------------------------- */
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#define ETHMACRST (1 << 14)
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#define OTGFSRST (1 << 12)
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/* --- RCC_CFGR2 values ---------------------------------------------------- */
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/* I2S3SRC: I2S3 clock source */
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#define I2S3SRC_SYSCLK 0x0
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#define I2S3SRC_PLL3_VCO_CLK 0x1
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/* I2S2SRC: I2S2 clock source */
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#define I2S2SRC_SYSCLK 0x0
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#define I2S2SRC_PLL3_VCO_CLK 0x1
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/* PREDIV1SRC: PREDIV1 entry clock source */
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#define PREDIV1SRC_HSE_CLK 0x0
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#define PREDIV1SRC_PLL2_CLK 0x1
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#define PLL2MUL (1 << 0)
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#define PREDIV2 (1 << 0)
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#define PREDIV1 (1 << 0)
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/* PLL3MUL: PLL3 multiplication factor */
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#define PLL3MUL_PLL3_CLK_MUL8 0x6
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#define PLL3MUL_PLL3_CLK_MUL9 0x7
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#define PLL3MUL_PLL3_CLK_MUL10 0x8
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#define PLL3MUL_PLL3_CLK_MUL11 0x9
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#define PLL3MUL_PLL3_CLK_MUL12 0xa
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#define PLL3MUL_PLL3_CLK_MUL13 0xb
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#define PLL3MUL_PLL3_CLK_MUL14 0xc
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#define PLL3MUL_PLL3_CLK_MUL16 0xe
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#define PLL3MUL_PLL3_CLK_MUL20 0xf
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/* PLL2MUL: PLL2 multiplication factor */
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#define PLL2MUL_PLL2_CLK_MUL8 0x6
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#define PLL2MUL_PLL2_CLK_MUL9 0x7
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#define PLL2MUL_PLL2_CLK_MUL10 0x8
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#define PLL2MUL_PLL2_CLK_MUL11 0x9
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#define PLL2MUL_PLL2_CLK_MUL12 0xa
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#define PLL2MUL_PLL2_CLK_MUL13 0xb
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#define PLL2MUL_PLL2_CLK_MUL14 0xc
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#define PLL2MUL_PLL2_CLK_MUL16 0xe
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#define PLL2MUL_PLL2_CLK_MUL20 0xf
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/* PREDIV2: PREDIV2 division factor */
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#define PREDIV2_NODIV 0x0
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#define PREDIV2_DIV2 0x1
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#define PREDIV2_DIV3 0x2
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#define PREDIV2_DIV4 0x3
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#define PREDIV2_DIV5 0x4
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#define PREDIV2_DIV6 0x5
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#define PREDIV2_DIV7 0x6
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#define PREDIV2_DIV8 0x7
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#define PREDIV2_DIV9 0x8
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#define PREDIV2_DIV10 0x9
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#define PREDIV2_DIV11 0xa
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#define PREDIV2_DIV12 0xb
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#define PREDIV2_DIV13 0xc
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#define PREDIV2_DIV14 0xd
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#define PREDIV2_DIV15 0xe
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#define PREDIV2_DIV16 0xf
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/* --- Function prototypes ------------------------------------------------- */
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typedef enum {
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PLL, HSE, HSI, LSE, LSI
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} osc_t;
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void rcc_osc_ready_int_clear(osc_t osc);
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void rcc_osc_ready_int_enable(osc_t osc);
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void rcc_osc_ready_int_disable(osc_t osc);
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int rcc_osc_ready_int_flag(osc_t osc);
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void rcc_css_int_clear(void);
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int rcc_css_int_flag(void);
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void rcc_wait_for_osc_ready(osc_t osc);
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void rcc_osc_on(osc_t osc);
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void rcc_osc_off(osc_t osc);
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void rcc_css_enable(void);
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void rcc_css_disable(void);
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void rcc_osc_bypass_enable(osc_t osc);
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void rcc_osc_bypass_disable(osc_t osc);
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
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void rcc_set_sysclk_source(u32 clk);
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void rcc_set_pll_multiplication_factor(u32 mul);
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void rcc_set_pll_source(u32 pllsrc);
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void rcc_set_pllxtpre(u32 pllxtpre);
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void rcc_set_adcpre(u32 adcpre);
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void rcc_set_ppre2(u32 ppre2);
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void rcc_set_ppre1(u32 ppre1);
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void rcc_set_hpre(u32 hpre);
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u32 rcc_get_system_clock_source(int i);
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void rcc_clock_setup_in_hsi_out_64mhz(void);
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void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
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#endif
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