243 lines
7.2 KiB
C
243 lines
7.2 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_RCC_H
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#define LIBOPENSTM32_RCC_H
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#include <libopenstm32.h>
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/* RCC registers */
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/* Note: Registers marked (**) only exist in "connectivity line" STM32s. */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
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#define RCC_CIR MMIO32(RCC_BASE + 0x08)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
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#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
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#define RCC_CSR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */
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#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */
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/* --- RCC_CR values ------------------------------------------------------- */
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/* Note: Bits marked (**) only exist in "connectivity line" STM32s. */
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#define HSION (1 << 0)
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#define HSIRDY (1 << 1)
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#define HSEON (1 << 16)
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#define HSERDY (1 << 17)
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#define HSEBYP (1 << 18)
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#define CSSON (1 << 19)
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#define PLLON (1 << 24)
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#define PLLRDY (1 << 25)
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#define PLL2ON (1 << 26) /* (**) */
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#define PLL2RDY (1 << 27) /* (**) */
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#define PLL3ON (1 << 28) /* (**) */
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#define PLL3RDY (1 << 29) /* (**) */
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/* --- RCC_CFGR values ----------------------------------------------------- */
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/* SW: System clock switch */
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#define SW_SYSCLKSEL_HSICLK 0x0
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#define SW_SYSCLKSEL_HSECLK 0x1
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#define SW_SYSCLKSEL_PLLCLK 0x2
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/* SWS: System clock switch status: Uses same bit definitions as SW. */
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/* HPRE: AHB prescaler */
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#define HPRE_SYSCLK 0x0
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#define HPRE_SYSCLK_DIV2 0x8
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#define HPRE_SYSCLK_DIV4 0x9
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#define HPRE_SYSCLK_DIV8 0xa
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#define HPRE_SYSCLK_DIV16 0xb
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#define HPRE_SYSCLK_DIV64 0xc
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#define HPRE_SYSCLK_DIV128 0xd
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#define HPRE_SYSCLK_DIV256 0xe
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#define HPRE_SYSCLK_DIV512 0xf
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/* PPRE1: APB low-speed prescaler (APB1) */
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#define PPRE1_HCLK 0x0
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#define PPRE1_HCLK_DIV2 0x4
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#define PPRE1_HCLK_DIV4 0x5
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#define PPRE1_HCLK_DIV8 0x6
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#define PPRE1_HCLK_DIV16 0x7
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define PPRE2_HCLK 0x0
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#define PPRE2_HCLK_DIV2 0x4
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#define PPRE2_HCLK_DIV4 0x5
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#define PPRE2_HCLK_DIV8 0x6
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#define PPRE2_HCLK_DIV16 0x7
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/* ADCPRE: ADC prescaler */
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#define ADCPRE_PLCLK2_DIV2 0x0
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#define ADCPRE_PLCLK2_DIV4 0x1
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#define ADCPRE_PLCLK2_DIV6 0x2
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#define ADCPRE_PLCLK2_DIV8 0x3
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/* PLLSRC: PLL entry clock source */
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#define PLLSRC_HSI_CLKDIV2 0x0
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#define PLLSRC_HSE_CLK 0x1
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/* PLLXTPRE: HSE divider for PLL entry */
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#define PLLXTPRE_HSE_CLK 0x0
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#define PLLXTPRE_HSE_CLK_DIV2 0x1
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/* PLLMUL: PLL multiplication factor */
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#define PLLMUL_PLLCLK_MUL2 0x0
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#define PLLMUL_PLLCLK_MUL3 0x1
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#define PLLMUL_PLLCLK_MUL4 0x2
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#define PLLMUL_PLLCLK_MUL5 0x3
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#define PLLMUL_PLLCLK_MUL6 0x4
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#define PLLMUL_PLLCLK_MUL7 0x5
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#define PLLMUL_PLLCLK_MUL8 0x6
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#define PLLMUL_PLLCLK_MUL9 0x7
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#define PLLMUL_PLLCLK_MUL10 0x8
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#define PLLMUL_PLLCLK_MUL11 0x9
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#define PLLMUL_PLLCLK_MUL12 0xa
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#define PLLMUL_PLLCLK_MUL13 0xb
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#define PLLMUL_PLLCLK_MUL14 0xc
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#define PLLMUL_PLLCLK_MUL15 0xd
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#define PLLMUL_PLLCLK_MUL16 0xe
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// #define PLLMUL_PLLCLK_MUL16 0xf /* Errata? 17? */
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/* USBPRE: USB prescaler */
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#define USBPRE_PLLCLK_DIV1_5 0x0
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#define USBPRE_PLLCLK 0x1
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/* MCO: Microcontroller clock output */
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#define MCO_NOCLK 0x0
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#define MCO_SYSCLK 0x4
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#define MCO_HSICLK 0x5
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#define MCO_HSECLK 0x6
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#define MCO_PLLCLK_DIV2 0x7
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#define MCO_PLL2CLK 0x8
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#define MCO_PLL3CLK_DIV2 0x9
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#define MCO_XT1 0xa
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#define MCO_PLL3 0xb
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/* --- RCC_CIR values ------------------------------------------------------ */
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/* Note: Bits marked (**) only exist in "connectivity line" STM32s. */
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/* OSC ready interrupt flag bits */
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#define LSIRDYF (1 << 0)
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#define LSERDYF (1 << 1)
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#define HSIRDYF (1 << 2)
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#define HSERDYF (1 << 3)
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#define PLLRDYF (1 << 4)
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#define PLL2RDYF (1 << 5) /* (**) */
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#define PLL3RDYF (1 << 6) /* (**) */
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/* Clock security system interrupt flag bit */
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#define CSSF (1 << 7)
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/* OSC ready interrupt enable bits */
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#define LSIRDYIE (1 << 8)
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#define LSERDYIE (1 << 9)
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#define HSIRDYIE (1 << 10)
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#define HSERDYIE (1 << 11)
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#define PLLRDYIE (1 << 12)
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#define PLL2RDYIE (1 << 13) /* (**) */
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#define PLL3RDYIE (1 << 14) /* (**) */
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/* OSC ready interrupt clear bits */
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#define LSIRDYC (1 << 16)
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#define LSERDYC (1 << 17)
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#define HSIRDYC (1 << 18)
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#define HSERDYC (1 << 19)
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#define PLLRDYC (1 << 20)
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#define PLL2RDYC (1 << 21) /* (**) */
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#define PLL3RDYC (1 << 22) /* (**) */
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/* Clock security system interrupt clear bit */
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#define CSSC (1 << 23)
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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/* Note: Bits marked (**) are reserved in "connectivity line" STM32s. */
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#define AFIOEN (1 << 0)
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#define IOPAEN (1 << 2)
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#define IOPBEN (1 << 3)
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#define IOPCEN (1 << 4)
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#define IOPDEN (1 << 5)
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#define IOPEEN (1 << 6)
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#define IOPFEN (1 << 7) /* (**) */
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#define IOPGEN (1 << 8) /* (**) */
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#define ADC1EN (1 << 9)
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#define ADC2EN (1 << 10)
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#define TIM1EN (1 << 11)
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#define SPI1EN (1 << 12)
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#define USART1EN (1 << 14)
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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/* Note: Bit marked (**) are reserved in "connectivity line" STM32s. */
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#define TIM2EN (1 << 0)
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#define TIM3EN (1 << 1)
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#define TIM4EN (1 << 2)
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#define TIM5EN (1 << 3)
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#define TIM6EN (1 << 4)
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#define TIM7EN (1 << 5)
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#define WWDGEN (1 << 11)
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#define SPI2EN (1 << 14)
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#define SPI3EN (1 << 15)
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#define USART2EN (1 << 17)
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#define USART3EN (1 << 18)
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#define USART4EN (1 << 19)
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#define USART5EN (1 << 20)
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#define I2C1EN (1 << 21)
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#define I2C2EN (1 << 22)
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#define USBEN (1 << 23) /* (**) */
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#define CANEN (1 << 25) /* Alias for CAN1EN */
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#define CAN1EN (1 << 25)
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#define CAN2EN (1 << 26) /* (**) */
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#define BKPEN (1 << 27)
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#define PWREN (1 << 28)
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#define DACEN (1 << 29)
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/* --- RCC_BDCR values -------------------------------------------------- */
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#define LSEON (1 << 0)
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#define LSERDY (1 << 1)
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#define LSEBYP (1 << 2)
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#define RTCEN (1 << 15)
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#define BDRST (1 << 16)
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/* --- RCC_CSR values -------------------------------------------------- */
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#define LSION (1 << 0)
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#define LSIRDY (1 << 1)
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#define RMVF (1 << 24)
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#define PINRSTF (1 << 26)
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#define PORRSTF (1 << 27)
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#define SFTRSTF (1 << 28)
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#define IWDGRSTF (1 << 29)
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#define WWDGRSTF (1 << 30)
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#define LPWRRSTF (1 << 31)
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typedef enum {
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PLL, HSE, HSI, LSE, LSI
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} osc_t;
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#endif
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