45e14a7bd3
Lots of common stuff, but the F7 fixed the temperature sensor randomness that the f4 had. Separate the definitions properly.
120 lines
4.1 KiB
C
120 lines
4.1 KiB
C
/** @defgroup adc_defines ADC Defines
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@brief <b>Defined Constants and Types for the STM32F4xx Analog to Digital
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Converters</b>
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@ingroup STM32F4xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2019
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Matthew Lai <m@matthewlai.ca>
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@author @htmlonly © @endhtmlonly 2009
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Edward Cheeseman <evbuilder@users.sourceforge.net>
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@date 31 August 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Matthew Lai <m@matthewlai.ca>
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* Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_ADC_H
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#define LIBOPENCM3_ADC_H
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#include <libopencm3/stm32/common/adc_common_v1_multi.h>
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/** @defgroup adc_channel ADC Channel Numbers
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* @ingroup adc_defines
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* Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18!
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*@{*/
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#define ADC_CHANNEL_TEMP_F40 16
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#define ADC_CHANNEL_TEMP_F42 18
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#define ADC_CHANNEL_VREF 17
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#define ADC_CHANNEL_VBAT 18
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/**@}*/
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/* --- Convenience macros -------------------------------------------------- */
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/* EXTSEL[3:0]: External event selection for regular group. */
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/****************************************************************************/
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/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group
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@ingroup adc_defines
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@{*/
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/** Timer 1 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24)
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/** Timer 1 Compare Output 2 */
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#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24)
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/** Timer 1 Compare Output 3 */
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#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24)
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/** Timer 2 Compare Output 2 */
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#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24)
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/** Timer 2 Compare Output 3 */
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#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24)
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/** Timer 2 Compare Output 4 */
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#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24)
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/** Timer 2 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24)
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/** Timer 3 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24)
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/** Timer 3 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24)
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/** Timer 4 Compare Output 4 */
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#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24)
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/** Timer 5 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24)
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/** Timer 5 Compare Output 2 */
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#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24)
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/** Timer 5 Compare Output 3 */
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#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24)
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/** Timer 8 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24)
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/** Timer 8 TRGO Event */
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#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24)
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/** EXTI Line 11 Event */
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#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24)
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/**@}*/
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/* JEXTSEL[3:0]: External event selection for injected group. */
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/****************************************************************************/
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/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group
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@ingroup adc_defines
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@{*/
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#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16)
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#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16)
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#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16)
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#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16)
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#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16)
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#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16)
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#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16)
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#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16)
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#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16)
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#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16)
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#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16)
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#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16)
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#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16)
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#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16)
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#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16)
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#define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16)
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/**@}*/
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#endif
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