7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
178 lines
5.0 KiB
C
178 lines
5.0 KiB
C
/* big fat FIXME: this should use a consistent structure, and reference
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* functionality from libopencm3 instead of copypasting.
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*
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* particularly unimplemented features are FIXME'd extra
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* */
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/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant
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* of the symbols efm32lib needs of CMSIS. */
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#ifndef OPENCMSIS_CORECM3_H
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#define OPENCMSIS_CORECM3_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/cm3/memorymap.h>
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#include <libopencm3/cm3/systick.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/scb.h>
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/* needed by system_efm32.h:196, guessing */
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#define __INLINE inline
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/* new since emlib 3.0 */
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#define __STATIC_INLINE static inline
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/* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the
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* libopencm3 ones, "volatile" is all that's missing. */
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#define __IO volatile
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#define __O volatile
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#define __I volatile
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/* -> style access for what is defined in libopencm3/stm32/f1/scb.h /
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* cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */
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/* from cm3/scb.h */
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#define SCB_SCR_SLEEPDEEP_Msk SCB_SCR_SLEEPDEEP
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/* structure as in, for example,
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* DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from
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* libopencm3/cm3/scb.h. FIXME incomplete. */
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typedef struct {
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__IO uint32_t CPUID;
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__IO uint32_t ICSR;
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__IO uint32_t VTOR;
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__IO uint32_t AIRCR;
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__IO uint32_t SCR;
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__IO uint32_t CCR;
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__IO uint8_t SHPR[12]; /* FIXME: how is this properly indexed? */
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__IO uint32_t SHCSR;
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} SCB_TypeDef;
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#define SCB ((SCB_TypeDef *) SCB_BASE)
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/* needed by efm32_emu.h, guessing and taking the implementation used in
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* lightswitch-interrupt.c */
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#define __WFI() __asm__("wfi")
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/* needed by efm32_cmu.h, probably it's just what gcc provides anyway */
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#define __CLZ(div) __builtin_clz(div)
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/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev
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* instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106
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*/
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#define __REV(x) __builtin_bswap32(x)
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/* stubs for efm32_dbg.h */
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typedef struct {
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uint32_t DHCSR;
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uint32_t DEMCR; /* needed by efm32tg stk trace.c */
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} CoreDebug_TypeDef;
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/* FIXME let's just hope writes to flash are protected */
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#define CoreDebug ((CoreDebug_TypeDef *) 0)
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#define CoreDebug_DHCSR_C_DEBUGEN_Msk 0
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#define CoreDebug_DEMCR_TRCENA_Msk 0
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/* stubs for efm32_dma */
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static inline void NVIC_ClearPendingIRQ(uint8_t irqn)
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{
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nvic_clear_pending_irq(irqn);
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}
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static inline void NVIC_EnableIRQ(uint8_t irqn)
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{
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nvic_enable_irq(irqn);
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}
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static inline void NVIC_DisableIRQ(uint8_t irqn)
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{
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nvic_disable_irq(irqn);
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}
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/* stubs for efm32_int. FIXME: how do they do that? nvic documentation in the
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* efm32 core manual doesn't tell anything of a global on/off switch */
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#define __enable_irq() 1
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#define __disable_irq() 1
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/* stubs for efm32_mpu FIXME */
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#define SCB_SHCSR_MEMFAULTENA_Msk 0
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typedef struct {
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uint32_t CTRL;
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uint32_t RNR;
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uint32_t RBAR;
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uint32_t RASR;
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} MPU_TypeDef;
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/* FIXME struct at NULL */
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#define MPU ((MPU_TypeDef *) 0)
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#define MPU_CTRL_ENABLE_Msk 0
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#define MPU_RASR_XN_Pos 0
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#define MPU_RASR_AP_Pos 0
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#define MPU_RASR_TEX_Pos 0
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#define MPU_RASR_S_Pos 0
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#define MPU_RASR_C_Pos 0
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#define MPU_RASR_B_Pos 0
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#define MPU_RASR_SRD_Pos 0
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#define MPU_RASR_SIZE_Pos 0
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#define MPU_RASR_ENABLE_Pos 0
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/* required for the blink example */
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/* if if (SysTick_Config(CMU_ClockFreqGet(cmuClock_CORE) / 1000)) while (1) ;
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* configures the sys ticks to 1ms, then the argument to SysTick_Config
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* describes how many cycles to wait between two systicks.
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*
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* the endless loop part looks like an "if it returns an error condition,
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* rather loop here than continue"; every other solution would involve things
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* that are dark magic to my understanding.
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*
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* implementation more or less copypasted from lib/stm32/systick.c, FIXME until
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* the generic cm3 functionality is moved out from stm32 and can be used here
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* easily (systick_set_reload, systick_interrupt_enable, systick_counter_enable
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* and systick_set_clocksource).
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*
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* modified for CMSIS style array as the powertest example needs it.
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* */
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/* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */
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typedef struct {
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uint32_t CTRL;
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uint32_t LOAD;
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uint32_t VAL;
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uint32_t CALIB;
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} SysTick_TypeDef;
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#define SysTick ((SysTick_TypeDef *) SYS_TICK_BASE)
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static inline uint32_t SysTick_Config(uint32_t n_ticks)
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{
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/* constant from systick_set_reload -- as this returns something that's
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* not void, this is the only possible error condition */
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if (n_ticks & ~0x00FFFFFF) {
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return 1;
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}
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systick_set_reload(n_ticks);
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systick_set_clocksource(true);
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systick_interrupt_enable();
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systick_counter_enable();
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return 0;
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}
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/* stubs for efm32tg stk trace.c */
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typedef struct {
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uint32_t LAR;
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uint32_t TCR;
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} ITM_TypeDef;
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/* FIXME struct at NULL */
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#define ITM ((ITM_TypeDef *) 0)
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/* blink.h expects the isr for systicks to be named SysTick_Handler. with this,
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* its Systick_Handler function gets renamed to the weak symbol exported by
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* vector.c */
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#define SysTick_Handler sys_tick_handler
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/* FIXME: this needs to be done for all of the 14 hard vectors */
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#include <libopencmsis/dispatch/irqhandlers.h>
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#endif
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