53302439df
Updates to a base set of includes to map to the h7 include files which are mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO). Custom files that have been implemented from the datasheet/ref manual include the memory map, RCC, PWR definitions, and irq.json file for generation of nvic files for interrupt mapping. Additional functionality, especially PLL and tweaks for non-F7 compatible implementations coming in future commits. Added documentation tree configuration. Reviewed-by: Karl Palsson <karlp@tweak.net.au> Changed dmaX_streamX to dmaX_strX in a few places for consistency
158 lines
5.5 KiB
C
158 lines
5.5 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- STM32H7 specific peripheral definitions ----------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE 0x40000000U
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#define PERIPH_BASE_APB1 0x40000000U
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#define PERIPH_BASE_APB2 0x40010000U
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#define PERIPH_BASE_APB3 0x50000000U
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#define PERIPH_BASE_AHB1 0x40020000U
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#define PERIPH_BASE_AHB2 0x48020000U
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#define PERIPH_BASE_AHB3 0x51000000U
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#define PERIPH_BASE_AHB4 0x58000000U
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/* Table 8: Register boundary addresses */
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/* AHB4 Peripherals */
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#define GPIO_PORT_A_BASE 0x58020000U
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#define GPIO_PORT_B_BASE 0x58020400U
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#define GPIO_PORT_C_BASE 0x58020800U
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#define GPIO_PORT_D_BASE 0x58020C00U
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#define GPIO_PORT_E_BASE 0x58021000U
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#define GPIO_PORT_F_BASE 0x58021400U
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#define GPIO_PORT_G_BASE 0x58021800U
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#define GPIO_PORT_H_BASE 0x58021C00U
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#define GPIO_PORT_I_BASE 0x58022000U
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#define GPIO_PORT_J_BASE 0x58022400U
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#define GPIO_PORT_K_BASE 0x58022800U
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#define RCC_BASE 0x58024400U
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#define POWER_CONTROL_BASE 0x58024800U
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#define CRC_BASE 0x58024C00U
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#define BDMA_BASE 0x58025400U
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#define DMAMUX2_BASE 0x58025800U
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#define ADC3_BASE 0x58026000U
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#define HSEM_BASE 0x58026400U
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/* APB4 Peripherals */
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#define SAI4_BASE 0x58005400U
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#define IWDG1_BASE 0x58004800U
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#define RTC_BASE 0x58004000U
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#define VREF_BASE 0x58003C00U
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#define COMP1_BASE 0x58003800U
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#define LPTIM5_BASE 0x58003000U
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#define LPTIM4_BASE 0x58002C00U
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#define LPTIM3_BASE 0x58002800U
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#define LPTIM2_BASE 0x58002400U
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#define I2C4_BASE 0x58001C00U
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#define SPI6_BASE 0x58001400U
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#define LPUART1_BASE 0x58000C00U
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#define SYSCFG_BASE 0x58000400U
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#define EXTI_BASE 0x58000000U
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/* AHB3 Peripherals */
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#define DELAY_SDMMC1_BASE 0x52008000U
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#define SDMMC1_BASE 0x52007000U
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#define DELAY_QSPI_BASE 0x52006000U
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#define QUADSPI_BASE 0x52005000U
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#define FMC_BASE 0x52004000U
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#define JPEG_BASE 0x52003000U
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#define FLASH_MEM_INTERFACE_BASE 0x52002000U
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#define CHROMART_BASE 0x52001000U
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#define MDMA_BASE 0x52000000U
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#define GPV_BASE 0x51000000U
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/* APB3 Peripherals */
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#define WWDG1_BASE 0x50003000U
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#define LTDC_BASE 0x50001000U
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/* AHB2 Peripherals */
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#define DELAY_SDMMC2_BASE 0x48022800U
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#define SDMMC2_BASE 0x48022400U
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#define RNG_BASE 0x48021800U
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#define HASH_BASE 0x48021400U
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#define CRYPTO_BASE 0x48021000U
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#define DCMI_BASE 0x48020000U
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/* AHB1 Peripherals */
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#define USB2_OTG_FS_BASE 0x40080000U
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#define USB1_OTG_HS_BASE 0x40040000U
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#define ETHERNET_MAC_BASE 0x40028000U
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#define ADC1_ADC2_BASE 0x40022000U
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#define DMAMUX1_BASE 0x40020800U
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#define DMA2_BASE 0x40020400U
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#define DMA1_BASE 0x40020000U
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/* APB2 Peripherals */
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#define HRTIM_BASE 0x40017400U
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#define DFSDM1_BASE 0x40017000U
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#define SAI3_BASE 0x40016000U
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#define SAI2_BASE 0x40015C00U
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#define SAI1_BASE 0x40015800U
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#define SPI5_BASE 0x40015000U
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#define TIM17_BASE 0x40014800U
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#define TIM16_BASE 0x40014400U
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#define TIM15_BASE 0x40014000U
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#define SPI4_BASE 0x40013400U
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#define SPI1_BASE 0x40013000U
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#define USART6_BASE 0x40011400U
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#define USART1_BASE 0x40011000U
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#define TIM8_BASE 0x40010400U
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#define TIM1_BASE 0x40010000U
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/* APB1 Peripherals */
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#define CAN_MSG_BASE 0x4000AC00U
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#define CAN_CCU_BASE 0x4000A800U
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#define FDCAN2_BASE 0x4000A400U
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#define FDCAN1_BASE 0x4000A000U
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#define MDIOS_BASE 0x40009400U
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#define OPAMP_BASE 0x40009000U
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#define SWPMI_BASE 0x40008800U
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#define CRS_BASE 0x40008400U
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#define UART8_BASE 0x40007C00U
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#define UART7_BASE 0x40007800U
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#define DAC_BASE 0x40007400U
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#define HDMI_CEC_BASE 0x40006C00U
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#define I2C3_BASE 0x40005C00U
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#define I2C2_BASE 0x40005800U
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#define I2C1_BASE 0x40005400U
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#define UART5_BASE 0x40005000U
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#define UART4_BASE 0x40004C00U
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#define USART3_BASE 0x40004800U
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#define USART2_BASE 0x40004400U
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#define SPDIFRX1_BASE 0x40004000U
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#define SPI3_BASE 0x40003C00U
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#define SPI2_BASE 0x40003800U
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#define LPTIM1_BASE 0x40002400U
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#define TIM14_BASE 0x40002000U
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#define TIM13_BASE 0x40001C00U
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#define TIM12_BASE 0x40001800U
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#define TIM7_BASE 0x40001400U
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#define TIM6_BASE 0x40001000U
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#define TIM5_BASE 0x40000C00U
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#define TIM4_BASE 0x40000800U
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#define TIM3_BASE 0x40000400U
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#define TIM2_BASE 0x40000000U
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#endif
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