53302439df
Updates to a base set of includes to map to the h7 include files which are mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO). Custom files that have been implemented from the datasheet/ref manual include the memory map, RCC, PWR definitions, and irq.json file for generation of nvic files for interrupt mapping. Additional functionality, especially PLL and tweaks for non-F7 compatible implementations coming in future commits. Added documentation tree configuration. Reviewed-by: Karl Palsson <karlp@tweak.net.au> Changed dmaX_streamX to dmaX_strX in a few places for consistency
80 lines
2.4 KiB
C
80 lines
2.4 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Brian Viele <vielster@allocor.tech>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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/**@{*/
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/** @defgroup pwr_registers PWR Registers
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* @ingroup STM32H_pwr_defines
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@{*/
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/** Power control register. */
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#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)
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/** Power control/status register. */
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#define PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04)
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/** Power control register 2. */
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#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08)
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/** Power control register 3. */
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#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x0C)
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/** CPU Power control register 3. */
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#define PWR_CPUCR MMIO32(POWER_CONTROL_BASE + 0x10)
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/** D3 Domain Power Control register. */
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#define PWR_D3CR MMIO32(POWER_CONTROL_BASE + 0x18)
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/** Wakeup Domain Power Control register. */
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#define PWR_WKUPCR MMIO32(POWER_CONTROL_BASE + 0x20)
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/*@}*/
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/** VOS[15:14]: Regulator voltage scaling output selection */
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#define PWR_CR1_SVOS_SHIFT 14
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#define PWR_CR1_SVOS_SCALE_3 (0x3)
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#define PWR_CR1_SVOS_SCALE_4 (0x2)
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#define PWR_CR1_SVOS_SCALE_5 (0x1)
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#define PWR_CR1_SVOS_MASK (0x3)
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/** DBP[8]: Disable backup domain write protection. */
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#define PWR_CR1_DBP (1 << 8)
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/** PVDO: PVD output */
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#define PWR_CSR1_PVDO (1 << 4)
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/* --- Function prototypes ------------------------------------------------- */
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enum pwr_svos_scale {
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PWR_SCALE3 = PWR_CR1_SVOS_SCALE_3 << PWR_CR1_SVOS_SHIFT,
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PWR_SCALE4 = PWR_CR1_SVOS_SCALE_4 << PWR_CR1_SVOS_SHIFT,
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PWR_SCALE5 = PWR_CR1_SVOS_SCALE_5 << PWR_CR1_SVOS_SHIFT,
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};
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BEGIN_DECLS
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void pwr_set_svos_scale(enum pwr_svos_scale scale);
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END_DECLS
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/**@}*/
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#endif
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