2975c3151a
lptimer peripheral is present on f4,f7,l0,l4,g0,g4 and prob others. Extract content from stm32l0 timer.h and make it usable by other chips.
104 lines
3.8 KiB
C
104 lines
3.8 KiB
C
/** @defgroup timer_defines Timer Defines
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@brief <b>libopencm3 Defined Constants and Types for the STM32L0xx Timers</b>
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@ingroup STM32L0xx_defines
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@version 1.0.0
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@date 17 May 2015
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@author @htmlonly © @endhtmlonly 2015 Robin Kreis <r.kreis@uni-bremen.de>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Robin Kreis <r.kreis@uni-bremen.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_TIMER_H
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#define LIBOPENCM3_TIMER_H
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#include <libopencm3/stm32/common/timer_common_all.h>
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/**@{*/
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/** Timer 2/21/22 option register (TIMx_OR) */
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#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50)
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#define TIM2_OR TIM_OR(TIM2)
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#define TIM21_OR TIM_OR(TIM21)
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#define TIM22_OR TIM_OR(TIM22)
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#define TIM2_OR_ETR_RMP_SHIFT 0
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#define TIM2_OR_ETR_RMP (7 << TIM2_OR_ETR_RMP_SHIFT)
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#define TIM2_OR_ETR_RMP_GPIO (0 << TIM2_OR_ETR_RMP_SHIFT)
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#define TIM2_OR_ETR_RMP_HSI48 (4 << TIM2_OR_ETR_RMP_SHIFT)
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#define TIM2_OR_ETR_RMP_LSE (5 << TIM2_OR_ETR_RMP_SHIFT)
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#define TIM2_OR_ETR_RMP_COMP2_OUT (6 << TIM2_OR_ETR_RMP_SHIFT)
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#define TIM2_OR_ETR_RMP_COMP1_OUT (7 << TIM2_OR_ETR_RMP_SHIFT)
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#define TIM2_OR_TI4_RMP_SHIFT 3
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#define TIM2_OR_TI4_RMP (3 << TIM2_OR_TI4_RMP_SHIFT)
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#define TIM2_OR_TI4_RMP_GPIO (0 << TIM2_OR_TI4_RMP_GPIO)
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#define TIM2_OR_TI4_RMP_COMP2_OUT (1 << TIM2_OR_TI4_RMP_GPIO)
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#define TIM2_OR_TI4_RMP_COMP1_OUT (2 << TIM2_OR_TI4_RMP_GPIO)
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#define TIM21_OR_ETR_RMP_SHIFT 0
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#define TIM21_OR_ETR_RMP (3 << TIM21_OR_ETR_RMP_SHIFT)
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#define TIM21_OR_ETR_RMP_GPIO (0 << TIM21_OR_ETR_RMP_SHIFT)
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#define TIM21_OR_ETR_RMP_COMP2_OUT (1 << TIM21_OR_ETR_RMP_SHIFT)
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#define TIM21_OR_ETR_RMP_COMP1_OUT (2 << TIM21_OR_ETR_RMP_SHIFT)
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#define TIM21_OR_ETR_RMP_LSE (3 << TIM21_OR_ETR_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_SHIFT 2
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#define TIM21_OR_TI1_RMP (7 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_GPIO (0 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_RTC_WAKEUP (1 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_HSE_RTC (2 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_MSI (3 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_LSE (4 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_LSI (5 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_COMP1_OUT (6 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI1_RMP_MCO (7 << TIM21_OR_TI1_RMP_SHIFT)
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#define TIM21_OR_TI2_RMP_SHIFT 5
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#define TIM21_OR_TI2_RMP (1 << TIM21_OR_TI2_RMP_SHIFT)
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#define TIM21_OR_TI2_RMP_GPIO (0 << TIM21_OR_TI2_RMP_SHIFT)
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#define TIM21_OR_TI2_RMP_COMP2_OUT (1 << TIM21_OR_TI2_RMP_SHIFT)
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#define TIM22_OR_ETR_RMP_SHIFT 0
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#define TIM22_OR_ETR_RMP (3 << TIM22_OR_ETR_RMP_SHIFT)
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#define TIM22_OR_ETR_GPIO (0 << TIM22_OR_ETR_RMP_SHIFT)
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#define TIM22_OR_ETR_COMP2_OUT (1 << TIM22_OR_ETR_RMP_SHIFT)
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#define TIM22_OR_ETR_COMP1_OUT (2 << TIM22_OR_ETR_RMP_SHIFT)
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#define TIM22_OR_ETR_LSE (3 << TIM22_OR_ETR_RMP_SHIFT)
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#define TIM22_OR_TI1_RMP_SHIFT 2
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#define TIM22_OR_TI1_RMP (3 << TIM22_OR_TI1_RMP_SHIFT)
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#define TIM22_OR_TI1_RMP_GPIO (0 << TIM22_OR_TI1_RMP_SHIFT)
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#define TIM22_OR_TI1_RMP_COMP2_OUT (1 << TIM22_OR_TI1_RMP_SHIFT)
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#define TIM22_OR_TI1_RMP_COMP1_OUT (2 << TIM22_OR_TI1_RMP_SHIFT)
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/**@}*/
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#endif
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/**@}*/
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