888fee1409
This drops a lot of now common definitions. This is still just prepratory work before using the v1-multi code itself.
191 lines
5.9 KiB
C
191 lines
5.9 KiB
C
/** @defgroup adc_defines ADC Defines
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@brief <b>Defined Constants and Types for the STM32L1xx Analog to
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Digital Converters</b>
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@ingroup STM32L1xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2013 Karl Palsson <karlp@remake.is>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Karl Palsson <karlp@remake.is>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_ADC_H
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#define LIBOPENCM3_ADC_H
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#include <libopencm3/stm32/common/adc_common_v1_multi.h>
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#define ADC_MAX_REGULAR_SEQUENCE 28
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/* 26 in L/M, but 32 in two banks for M+/H density */
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#define ADC_MAX_CHANNELS 32
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/* ADC sample time register 3 (ADC_SMPR3) */
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#define ADC_SMPR3(block) MMIO32((block) + 0x14)
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#define ADC1_SMPR3 ADC_SMPR3(ADC1)
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/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
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#define ADC_JOFR1(block) MMIO32((block) + 0x18)
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#define ADC_JOFR2(block) MMIO32((block) + 0x1c)
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#define ADC_JOFR3(block) MMIO32((block) + 0x20)
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#define ADC_JOFR4(block) MMIO32((block) + 0x24)
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/* ADC watchdog high threshold register (ADC_HTR) */
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#define ADC_HTR(block) MMIO32((block) + 0x28)
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/* ADC watchdog low threshold register (ADC_LTR) */
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#define ADC_LTR(block) MMIO32((block) + 0x2c)
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/* ADC regular sequence register 1 (ADC_SQR1) */
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#define ADC_SQR1(block) MMIO32((block) + 0x30)
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/* ADC regular sequence register 2 (ADC_SQR2) */
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#define ADC_SQR2(block) MMIO32((block) + 0x34)
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/* ADC regular sequence register 3 (ADC_SQR3) */
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#define ADC_SQR3(block) MMIO32((block) + 0x38)
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/* ADC regular sequence register 4 (ADC_SQR4) */
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#define ADC_SQR4(block) MMIO32((block) + 0x3c)
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#define ADC1_SQR4 ADC_SQR4(ADC1)
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/* ADC regular sequence register 5 (ADC_SQR5) */
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#define ADC_SQR5(block) MMIO32((block) + 0x40)
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#define ADC1_SQR5 ADC_SQR5(ADC1)
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/* ADC injected sequence register (ADC_JSQR) */
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#define ADC_JSQR(block) MMIO32((block) + 0x44)
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/* ADC injected data register x (ADC_JDRx) (x=1..4) */
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#define ADC_JDR1(block) MMIO32((block) + 0x48)
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#define ADC_JDR2(block) MMIO32((block) + 0x4c)
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#define ADC_JDR3(block) MMIO32((block) + 0x50)
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#define ADC_JDR4(block) MMIO32((block) + 0x54)
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/* ADC regular data register (ADC_DR) */
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#define ADC_DR(block) MMIO32((block) + 0x58)
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/* ADC sample time register 0 (ADC_SMPR0) (high/med+ only) */
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#define ADC_SMPR0(block) MMIO32((block) + 0x5c)
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#define ADC1_SMPR0 ADC_SMPR0(ADC1)
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/** @defgroup adc_channel ADC Channel Numbers
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* @ingroup adc_defines
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*
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*@{*/
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#define ADC_CHANNEL_TEMP ADC_CHANNEL16
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#define ADC_CHANNEL_VREF ADC_CHANNEL17
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/**@}*/
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/* --- ADC_SR values ------------------------------------------------------- */
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/****************************************************************************/
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/** @defgroup adc_sr_values ADC Status Register Flags
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* @ingroup adc_defines
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*
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*@{*/
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/* JCNR:*//** Injected channel not ready */
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#define ADC_SR_JCNR (1 << 9)
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/* RCNR:*//** Regular channel not ready */
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#define ADC_SR_RCNR (1 << 8)
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/* ADONS:*//** ADC ON status */
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#define ADC_SR_ADONS (1 << 6)
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/**@}*/
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/* --- ADC_CR1 values ------------------------------------------------------- */
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#define ADC_CR1_PDI (1 << 17)
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#define ADC_CR1_PDD (1 << 16)
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#define ADC_CR1_AWDCH_MAX 26
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/* EXTSEL[3:0]: External event selection for regular group. */
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/****************************************************************************/
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/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group
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@ingroup adc_defines
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@{*/
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#define ADC_CR2_EXTSEL_TIM9_CC2 (0 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM9_TRGO (1 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM2_CC3 (2 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM2_CC2 (3 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM3_TRGO (4 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM4_CC4 (5 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM2_TRGO (6 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM3_CC1 (7 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM3_CC3 (8 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM4_TRGO (9 << ADC_CR2_EXTSEL_SHIFT)
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#define ADC_CR2_EXTSEL_TIM6_TRGO (10 << ADC_CR2_EXTSEL_SHIFT)
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/* reserved.... */
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#define ADC_CR2_EXTSEL_EXTI11 (15 << ADC_CR2_EXTSEL_SHIFT)
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/**@}*/
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/* FIXME - JEXTSEL values here */
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/* FIXME- add the values here */
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#define ADC_CR2_DELS_SHIFT 4
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#define ADC_CR2_DELS_MASK 0x7
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#define ADC_CR2_ADC_CFG (1 << 2)
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/* --- ADC_SMPRx generic values -------------------------------------------- */
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/****************************************************************************/
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/* ADC_SMPRG ADC Sample Time Selection for Channels */
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/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
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@ingroup adc_defines
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@{*/
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#define ADC_SMPR_SMP_4CYC 0x0
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#define ADC_SMPR_SMP_9CYC 0x1
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#define ADC_SMPR_SMP_16CYC 0x2
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#define ADC_SMPR_SMP_24CYC 0x3
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#define ADC_SMPR_SMP_48CYC 0x4
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#define ADC_SMPR_SMP_96CYC 0x5
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#define ADC_SMPR_SMP_192CYC 0x6
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#define ADC_SMPR_SMP_384CYC 0x7
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/**@}*/
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#define ADC_SQR_MASK 0x1f
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#define ADC_SQR_MAX_CHANNELS_REGULAR 28 /* m+/h only, otherwise 27 */
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/** @defgroup adc_ccr_adcpre ADC Prescale
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@ingroup adc_defines
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@{*/
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#define ADC_CCR_ADCPRE_BY1 (0x0 << 16)
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#define ADC_CCR_ADCPRE_BY2 (0x1 << 16)
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#define ADC_CCR_ADCPRE_BY4 (0x2 << 16)
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/**@}*/
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#define ADC_CCR_ADCPRE_MASK (0x3 << 16)
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#define ADC_CCR_ADCPRE_SHIFT 16
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BEGIN_DECLS
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END_DECLS
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#endif
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