58f9909474
The MPU RASR AP table has a duplicate entries for Privileged ReadOnly and Usermode ReadOnly, in the source ARM document (Cortex M3 TRM) Remove the duplicate here. The MPU RASR Shareable, Bufferable and Cacheable bits are all individual bits, and none of the existing defines appear to even match the ARM documentation. Remove them, but leave the definitions of the bit positions. Reported by MightyPork on IRC
144 lines
4.4 KiB
C
144 lines
4.4 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @defgroup CM3_mpu_defines MPU Defines
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*
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* @brief <b>libopencm3 Cortex Memory Protection Unit</b>
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*
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* @ingroup CM3_defines
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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*
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* The MPU is available as an option in both ARMv6-M and ARMv7-M, but it has
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* more features in v7, particularly in the available attributes.
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*
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* For more information see the ARM Architecture reference manuals.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_MPU_H
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#define LIBOPENCM3_MPU_H
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#include <libopencm3/cm3/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- SCB: Registers ------------------------------------------------------ */
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/** @defgroup CM3_mpu_registers MPU Registers
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* @ingroup CM3_mpu_defines
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*
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*@{*/
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/** MPU_TYPE is alays available, even if the MPU is not implemented */
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#define MPU_TYPE MMIO32(MPU_BASE + 0x00)
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#define MPU_CTRL MMIO32(MPU_BASE + 0x04)
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#define MPU_RNR MMIO32(MPU_BASE + 0x08)
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#define MPU_RBAR MMIO32(MPU_BASE + 0x0C)
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#define MPU_RASR MMIO32(MPU_BASE + 0x10)
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/**@}*/
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/* --- MPU values ---------------------------------------------------------- */
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/** @defgroup CM3_mpu_type MPU TYPE register fields
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* @ingroup CM3_mpu_defines
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* The MPU_TYPE register is always avilable, even if the MPU is not implemented.
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* In that case, the DREGION field will read as 0.
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*@{*/
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/** v6m/v7m only support a unified MPU (IREGION always 0) */
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#define MPU_TYPE_IREGION_LSB 16
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#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB)
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/** DREGION is non zero if the MPU is available */
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#define MPU_TYPE_DREGION_LSB 8
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#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB)
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/** v6m/v7m only support a unifed MPU (Separate always 0) */
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#define MPU_TYPE_SEPARATE (1<<0)
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/**@}*/
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/** @defgroup CM3_mpu_ctrl MPU CTRL register fields
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* @ingroup CM3_mpu_defines
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* Defines for the Control Register.
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*@{*/
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#define MPU_CTRL_PRIVDEFENA (1<<2)
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#define MPU_CTRL_HFNMIENA (1<<1)
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#define MPU_CTRL_ENABLE (1<<0)
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/**@}*/
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/** @defgroup CM3_mpu_rnr MPU RNR register fields
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* @ingroup CM3_mpu_defines
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* Defines for the Region Number Register.
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*@{*/
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#define MPU_RNR_REGION_LSB 0
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#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB)
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/**@}*/
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/** @defgroup CM3_mpu_rbar MPU RBAR register fields
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* @ingroup CM3_mpu_defines
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* Defines for the Region Base Address Register.
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*@{*/
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/** minimum size supported is by writing all ones to ADDR, then reading back */
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#define MPU_RBAR_ADDR 0xFFFFFFE0
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#define MPU_RBAR_VALID (1<<4)
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#define MPU_RBAR_REGION_LSB 0
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#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB)
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/**@}*/
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/** @defgroup CM3_mpu_rasr MPU RASR register fields
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* @ingroup CM3_mpu_defines
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* Defines for the Region Attribute and Size Register.
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*@{*/
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#define MPU_RASR_ATTRS_LSB 16
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#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB)
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#define MPU_RASR_SRD_LSB 8
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#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB)
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#define MPU_RASR_SIZE_LSB 1
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#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_ENABLE (1 << 0)
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/** @defgroup mpu_rasr_attributes MPU RASR Attributes
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* @ingroup CM3_mpu_rasr
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* Not all attributes are available on v6m.
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*
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*@{*/
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#define MPU_RASR_ATTR_XN (1 << 28)
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#define MPU_RASR_ATTR_AP (7 << 24)
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#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24)
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#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24)
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#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24)
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#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24)
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#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24)
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#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24)
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#define MPU_RASR_ATTR_TEX (7 << 19)
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#define MPU_RASR_ATTR_S (1 << 18)
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#define MPU_RASR_ATTR_C (1 << 17)
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#define MPU_RASR_ATTR_B (1 << 16)
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#define MPU_RASR_ATTR_SCB (7 << 16)
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/**@}*/
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/**@}*/
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/* --- MPU functions ------------------------------------------------------- */
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BEGIN_DECLS
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END_DECLS
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/**@}*/
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#endif
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