62849f043c
Based on existing HSI code. Tested with f100c8, on custom board with no external crystals or resonators.
423 lines
15 KiB
C
423 lines
15 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */
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/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */
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/* --- RCC registers ------------------------------------------------------- */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
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#define RCC_CIR MMIO32(RCC_BASE + 0x08)
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
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#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
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#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
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#define RCC_CSR MMIO32(RCC_BASE + 0x24)
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#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */
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#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */
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/* --- RCC_CR values ------------------------------------------------------- */
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#define RCC_CR_PLL3RDY (1 << 29) /* (**) */
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#define RCC_CR_PLL3ON (1 << 28) /* (**) */
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#define RCC_CR_PLL2RDY (1 << 27) /* (**) */
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#define RCC_CR_PLL2ON (1 << 26) /* (**) */
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#define RCC_CR_PLLRDY (1 << 25)
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#define RCC_CR_PLLON (1 << 24)
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#define RCC_CR_CSSON (1 << 19)
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#define RCC_CR_HSEBYP (1 << 18)
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#define RCC_CR_HSERDY (1 << 17)
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#define RCC_CR_HSEON (1 << 16)
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/* HSICAL: [15:8] */
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/* HSITRIM: [7:3] */
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
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/* --- RCC_CFGR values ----------------------------------------------------- */
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/* MCO: Microcontroller clock output */
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#define RCC_CFGR_MCO_NOCLK 0x0
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#define RCC_CFGR_MCO_SYSCLK 0x4
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#define RCC_CFGR_MCO_HSICLK 0x5
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#define RCC_CFGR_MCO_HSECLK 0x6
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#define RCC_CFGR_RMCO_PLLCLK_DIV2 0x7
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#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */
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#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
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#define RCC_CFGR_MCO_XT1 0xa /* (**) */
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#define RCC_CFGR_MCO_PLL3 0xb /* (**) */
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/* USBPRE: USB prescaler (RCC_CFGR[22]) */
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#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
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#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
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/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
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#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0
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#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1
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/* PLLMUL: PLL multiplication factor */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
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#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
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// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
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/* TODO: conn. line differs. */
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/* PLLXTPRE: HSE divider for PLL entry */
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#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
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#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
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/* PLLSRC: PLL entry clock source */
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#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
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#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
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#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */
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/* ADCPRE: ADC prescaler */
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#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
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#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
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#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
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#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
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#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
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#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
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#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
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#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
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/* PPRE1: APB low-speed prescaler (APB1) */
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#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
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#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
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#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
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#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
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#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
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/* HPRE: AHB prescaler */
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#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
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#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
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#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
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#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
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#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
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#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
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#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
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#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
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#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
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/* SWS: System clock switch status */
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#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
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#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1
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#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
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/* SW: System clock switch */
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#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
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#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
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#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
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/* --- RCC_CIR values ------------------------------------------------------ */
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/* Clock security system interrupt clear bit */
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#define RCC_CIR_CSSC (1 << 23)
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/* OSC ready interrupt clear bits */
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#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */
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#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */
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#define RCC_CIR_PLLRDYC (1 << 20)
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#define RCC_CIR_HSERDYC (1 << 19)
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#define RCC_CIR_HSIRDYC (1 << 18)
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#define RCC_CIR_LSERDYC (1 << 17)
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#define RCC_CIR_LSIRDYC (1 << 16)
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/* OSC ready interrupt enable bits */
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#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */
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#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */
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#define RCC_CIR_PLLRDYIE (1 << 12)
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#define RCC_CIR_HSERDYIE (1 << 11)
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#define RCC_CIR_HSIRDYIE (1 << 10)
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#define RCC_CIR_LSERDYIE (1 << 9)
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#define RCC_CIR_LSIRDYIE (1 << 8)
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/* Clock security system interrupt flag bit */
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#define RCC_CIR_CSSF (1 << 7)
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/* OSC ready interrupt flag bits */
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#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */
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#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */
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#define RCC_CIR_PLLRDYF (1 << 4)
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#define RCC_CIR_HSERDYF (1 << 3)
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#define RCC_CIR_HSIRDYF (1 << 2)
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#define RCC_CIR_LSERDYF (1 << 1)
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#define RCC_CIR_LSIRDYF (1 << 0)
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/* --- RCC_APB2RSTR values ------------------------------------------------- */
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#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */
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#define RCC_APB2RSTR_USART1RST (1 << 14)
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#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */
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#define RCC_APB2RSTR_SPI1RST (1 << 12)
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#define RCC_APB2RSTR_TIM1RST (1 << 11)
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#define RCC_APB2RSTR_ADC2RST (1 << 10)
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#define RCC_APB2RSTR_ADC1RST (1 << 9)
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#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */
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#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */
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#define RCC_APB2RSTR_IOPERST (1 << 6)
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#define RCC_APB2RSTR_IOPDRST (1 << 5)
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#define RCC_APB2RSTR_IOPCRST (1 << 4)
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#define RCC_APB2RSTR_IOPBRST (1 << 3)
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#define RCC_APB2RSTR_IOPARST (1 << 2)
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#define RCC_APB2RSTR_AFIORST (1 << 0)
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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#define RCC_APB1RSTR_DACRST (1 << 29)
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#define RCC_APB1RSTR_PWRRST (1 << 28)
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#define RCC_APB1RSTR_BKPRST (1 << 27)
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#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */
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#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */
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#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */
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#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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#define RCC_APB1RSTR_I2C1RST (1 << 21)
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#define RCC_APB1RSTR_UART5RST (1 << 20)
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#define RCC_APB1RSTR_UART4RST (1 << 19)
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#define RCC_APB1RSTR_USART3RST (1 << 18)
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#define RCC_APB1RSTR_USART2RST (1 << 17)
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#define RCC_APB1RSTR_SPI3RST (1 << 15)
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#define RCC_APB1RSTR_SPI2RST (1 << 14)
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#define RCC_APB1RSTR_WWDGRST (1 << 11)
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#define RCC_APB1RSTR_TIM7RST (1 << 5)
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#define RCC_APB1RSTR_TIM6RST (1 << 4)
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#define RCC_APB1RSTR_TIM5RST (1 << 3)
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#define RCC_APB1RSTR_TIM4RST (1 << 2)
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#define RCC_APB1RSTR_TIM3RST (1 << 1)
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#define RCC_APB1RSTR_TIM2RST (1 << 0)
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/* --- RCC_AHBENR values --------------------------------------------------- */
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#define RCC_AHBENR_ETHMACENRX (1 << 16)
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#define RCC_AHBENR_ETHMACENTX (1 << 15)
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#define RCC_AHBENR_ETHMACEN (1 << 14)
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#define RCC_AHBENR_OTGFSEN (1 << 12)
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#define RCC_AHBENR_SDIOEN (1 << 10)
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#define RCC_AHBENR_FSMCEN (1 << 8)
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#define RCC_AHBENR_CRCEN (1 << 6)
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#define RCC_AHBENR_FLITFEN (1 << 4)
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#define RCC_AHBENR_SRAMEN (1 << 2)
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#define RCC_AHBENR_DMA2EN (1 << 1)
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#define RCC_AHBENR_DMA1EN (1 << 0)
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */
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#define RCC_APB2ENR_USART1EN (1 << 14)
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#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */
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#define RCC_APB2ENR_SPI1EN (1 << 12)
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#define RCC_APB2ENR_TIM1EN (1 << 11)
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#define RCC_APB2ENR_ADC2EN (1 << 10)
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#define RCC_APB2ENR_ADC1EN (1 << 9)
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#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */
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#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */
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#define RCC_APB2ENR_IOPEEN (1 << 6)
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#define RCC_APB2ENR_IOPDEN (1 << 5)
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#define RCC_APB2ENR_IOPCEN (1 << 4)
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#define RCC_APB2ENR_IOPBEN (1 << 3)
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#define RCC_APB2ENR_IOPAEN (1 << 2)
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#define RCC_APB2ENR_AFIOEN (1 << 0)
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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#define RCC_APB1ENR_DACEN (1 << 29)
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#define RCC_APB1ENR_PWREN (1 << 28)
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#define RCC_APB1ENR_BKPEN (1 << 27)
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#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */
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#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */
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#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */
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#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */
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#define RCC_APB1ENR_I2C2EN (1 << 22)
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#define RCC_APB1ENR_I2C1EN (1 << 21)
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#define RCC_APB1ENR_UART5EN (1 << 20)
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#define RCC_APB1ENR_UART4EN (1 << 19)
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#define RCC_APB1ENR_USART3EN (1 << 18)
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#define RCC_APB1ENR_USART2EN (1 << 17)
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#define RCC_APB1ENR_SPI3EN (1 << 15)
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#define RCC_APB1ENR_SPI2EN (1 << 14)
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#define RCC_APB1ENR_WWDGEN (1 << 11)
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#define RCC_APB1ENR_TIM7EN (1 << 5)
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#define RCC_APB1ENR_TIM6EN (1 << 4)
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#define RCC_APB1ENR_TIM5EN (1 << 3)
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#define RCC_APB1ENR_TIM4EN (1 << 2)
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#define RCC_APB1ENR_TIM3EN (1 << 1)
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#define RCC_APB1ENR_TIM2EN (1 << 0)
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/* --- RCC_BDCR values ----------------------------------------------------- */
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#define RCC_BDCR_BDRST (1 << 16)
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#define RCC_BDCR_RTCEN (1 << 15)
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/* RCC_BDCR[9:8]: RTCSEL */
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#define RCC_BDCR_LSEBYP (1 << 2)
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#define RCC_BDCR_LSERDY (1 << 1)
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#define RCC_BDCR_LSEON (1 << 0)
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/* --- RCC_CSR values ------------------------------------------------------ */
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#define RCC_CSR_LPWRRSTF (1 << 31)
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#define RCC_CSR_WWDGRSTF (1 << 30)
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#define RCC_CSR_IWDGRSTF (1 << 29)
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#define RCC_CSR_SFTRSTF (1 << 28)
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#define RCC_CSR_PORRSTF (1 << 27)
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#define RCC_CSR_PINRSTF (1 << 26)
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#define RCC_CSR_RMVF (1 << 24)
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#define RCC_CSR_LSIRDY (1 << 1)
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#define RCC_CSR_LSION (1 << 0)
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/* --- RCC_AHBRSTR values -------------------------------------------------- */
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#define RCC_AHBRSTR_ETHMACRST (1 << 14)
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#define RCC_AHBRSTR_OTGFSRST (1 << 12)
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/* --- RCC_CFGR2 values ---------------------------------------------------- */
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/* I2S3SRC: I2S3 clock source */
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#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0
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#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1
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/* I2S2SRC: I2S2 clock source */
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#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0
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#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1
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/* PREDIV1SRC: PREDIV1 entry clock source */
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#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0
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#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1
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#define RCC_CFGR2_PLL2MUL (1 << 0)
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#define RCC_CFGR2_PREDIV2 (1 << 0)
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#define RCC_CFGR2_PREDIV1 (1 << 0)
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/* PLL3MUL: PLL3 multiplication factor */
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe
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#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf
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/* PLL2MUL: PLL2 multiplication factor */
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
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#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
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/* PREDIV2: PREDIV2 division factor */
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#define RCC_CFGR2_PREDIV2_NODIV 0x0
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#define RCC_CFGR2_PREDIV2_DIV2 0x1
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#define RCC_CFGR2_PREDIV2_DIV3 0x2
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#define RCC_CFGR2_PREDIV2_DIV4 0x3
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#define RCC_CFGR2_PREDIV2_DIV5 0x4
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#define RCC_CFGR2_PREDIV2_DIV6 0x5
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#define RCC_CFGR2_PREDIV2_DIV7 0x6
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#define RCC_CFGR2_PREDIV2_DIV8 0x7
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#define RCC_CFGR2_PREDIV2_DIV9 0x8
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#define RCC_CFGR2_PREDIV2_DIV10 0x9
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#define RCC_CFGR2_PREDIV2_DIV11 0xa
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#define RCC_CFGR2_PREDIV2_DIV12 0xb
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#define RCC_CFGR2_PREDIV2_DIV13 0xc
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#define RCC_CFGR2_PREDIV2_DIV14 0xd
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#define RCC_CFGR2_PREDIV2_DIV15 0xe
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#define RCC_CFGR2_PREDIV2_DIV16 0xf
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/* --- Variable definitions ------------------------------------------------ */
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extern u32 rcc_ppre1_frequency;
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extern u32 rcc_ppre2_frequency;
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/* --- Function prototypes ------------------------------------------------- */
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typedef enum {
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PLL, HSE, HSI, LSE, LSI
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} osc_t;
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void rcc_osc_ready_int_clear(osc_t osc);
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void rcc_osc_ready_int_enable(osc_t osc);
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void rcc_osc_ready_int_disable(osc_t osc);
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int rcc_osc_ready_int_flag(osc_t osc);
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void rcc_css_int_clear(void);
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int rcc_css_int_flag(void);
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void rcc_wait_for_osc_ready(osc_t osc);
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void rcc_osc_on(osc_t osc);
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void rcc_osc_off(osc_t osc);
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void rcc_css_enable(void);
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void rcc_css_disable(void);
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void rcc_osc_bypass_enable(osc_t osc);
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void rcc_osc_bypass_disable(osc_t osc);
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
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void rcc_set_sysclk_source(u32 clk);
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void rcc_set_pll_multiplication_factor(u32 mul);
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void rcc_set_pll_source(u32 pllsrc);
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void rcc_set_pllxtpre(u32 pllxtpre);
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void rcc_set_adcpre(u32 adcpre);
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void rcc_set_ppre2(u32 ppre2);
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void rcc_set_ppre1(u32 ppre1);
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void rcc_set_hpre(u32 hpre);
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void rcc_set_usbpre(u32 usbpre);
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u32 rcc_get_system_clock_source(int i);
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void rcc_clock_setup_in_hsi_out_64mhz(void);
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void rcc_clock_setup_in_hsi_out_48mhz(void);
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/**
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* Maximum speed possible for F100 (Value Line) on HSI
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*/
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void rcc_clock_setup_in_hsi_out_24mhz(void);
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void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
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void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
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void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
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void rcc_backupdomain_reset(void);
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#endif
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