111 lines
3.6 KiB
C
111 lines
3.6 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM0_MPU_H
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#define LIBOPENCM3_CM0_MPU_H
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#ifndef CM0_PLUS
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#error "mpu is supported only on CM0+ architecture"
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#else
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#include <libopencm3/cm0/memorymap.h>
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#include <libopencm3/cm0/common.h>
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/* --- SCB: Registers ------------------------------------------------------ */
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#define MPU_TYPE MMIO32(MPU_BASE + 0x00)
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#define MPU_CTRL MMIO32(MPU_BASE + 0x04)
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#define MPU_RNR MMIO32(MPU_BASE + 0x08)
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#define MPU_RBAR MMIO32(MPU_BASE + 0x0C)
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#define MPU_RASR MMIO32(MPU_BASE + 0x10)
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/* --- MPU values ---------------------------------------------------------- */
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/* --- MPU_TYPE values ----------------------------------------------------- */
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#define MPU_TYPE_IREGION_LSB 16
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#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB)
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#define MPU_TYPE_DREGION_LSB 8
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#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB)
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#define MPU_TYPE_SEPARATE (1<<0)
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/* --- MPU_CTRL values ----------------------------------------------------- */
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#define MPU_CTRL_PRIVDEFENA (1<<2)
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#define MPU_CTRL_HFNMIENA (1<<1)
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#define MPU_CTRL_ENABLE (1<<0)
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/* --- MPU_RNR values ------------------------------------------------------ */
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#define MPU_RNR_REGION_LSB 0
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#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB)
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/* --- MPU_RBAR values ----------------------------------------------------- */
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#define MPU_RBAR_ADDR_LSB 8
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#define MPU_RBAR_ADDR (0x00FFFFFF << MPU_RBAR_REGION_LSB)
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#define MPU_RBAR_VALID (1<<4)
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#define MPU_RBAR_REGION_LSB 0
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#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB)
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/* --- MPU_RASR values ----------------------------------------------------- */
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#define MPU_RASR_ATTRS_LSB 16
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#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB)
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#define MPU_RASR_SRD_LSB 8
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#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB)
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#define MPU_RASR_SIZE_LSB 1
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#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_ENABLE (1 << 0)
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#define MPU_RASR_ATTR_XN (1 << 28)
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#define MPU_RASR_ATTR_AP (7 << 24)
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#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24)
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#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24)
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#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24)
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#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24)
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#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24)
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#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24)
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#define MPU_RASR_ATTR_AP_PRO_URO (7 << 24)
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#define MPU_RASR_ATTR_TEX (7 << 19)
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#define MPU_RASR_ATTR_S (1 << 18)
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#define MPU_RASR_ATTR_C (1 << 17)
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#define MPU_RASR_ATTR_B (1 << 16)
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#define MPU_RASR_ATTR_SCB (7 << 16)
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#define MPU_RASR_ATTR_SCB_SH_STRONG (0 << 16)
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#define MPU_RASR_ATTR_SCB_SH_DEVICE (1 << 16)
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#define MPU_RASR_ATTR_SCB_NSH_WT (2 << 16)
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#define MPU_RASR_ATTR_SCB_NSH_WB (3 << 16)
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#define MPU_RASR_ATTR_SCB_SH_STRONG (4 << 16)
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#define MPU_RASR_ATTR_SCB_SH_DEVICE (5 << 16)
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#define MPU_RASR_ATTR_SCB_SH_WT (6 << 16)
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#define MPU_RASR_ATTR_SCB_SH_WB (7 << 16)
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/* --- MPU functions ------------------------------------------------------- */
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BEGIN_DECLS
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END_DECLS
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#endif /* CM0_PLUS */
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#endif
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