27bc12de61
This unifies stm32f1, l1, and f4 convenience functions for adc. The code should be useable for f2 and f37x as well, but that needs hardware for testing, and there was no existing implementation. This is the reason for the "adc_common_v1.c" name, as trying to put all the different families into the common file name has become too cumbersome. All of the deprecated routines have been dropped, they've been marked deprecated for a very long time now, and porting them seemed unnecessary. This has been tested on f1, l1 and f4 discovery boards, and is based on some existing l1/f1 unification code from https://github.com/karlp/libopencm3/tree/rme_l1_master
423 lines
15 KiB
C
423 lines
15 KiB
C
/** @defgroup adc_defines ADC Defines
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@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital
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Converters</b>
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@ingroup STM32F1xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009
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Edward Cheeseman <evbuilder@users.sourceforge.net>
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@date 18 August 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_ADC_H
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#define LIBOPENCM3_ADC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/adc_common_v1.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
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#define ADC_JOFR1(block) MMIO32(block + 0x14)
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#define ADC_JOFR2(block) MMIO32(block + 0x18)
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#define ADC_JOFR3(block) MMIO32(block + 0x1c)
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#define ADC_JOFR4(block) MMIO32(block + 0x20)
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/* ADC watchdog high threshold register (ADC_HTR) */
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#define ADC_HTR(block) MMIO32(block + 0x24)
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/* ADC watchdog low threshold register (ADC_LTR) */
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#define ADC_LTR(block) MMIO32(block + 0x28)
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/* ADC regular sequence register 1 (ADC_SQR1) */
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#define ADC_SQR1(block) MMIO32(block + 0x2c)
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/* ADC regular sequence register 2 (ADC_SQR2) */
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#define ADC_SQR2(block) MMIO32(block + 0x30)
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/* ADC regular sequence register 3 (ADC_SQR3) */
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#define ADC_SQR3(block) MMIO32(block + 0x34)
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/* ADC injected sequence register (ADC_JSQR) */
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#define ADC_JSQR(block) MMIO32(block + 0x38)
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/* ADC injected data register x (ADC_JDRx) (x=1..4) */
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#define ADC_JDR1(block) MMIO32(block + 0x3c)
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#define ADC_JDR2(block) MMIO32(block + 0x40)
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#define ADC_JDR3(block) MMIO32(block + 0x44)
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#define ADC_JDR4(block) MMIO32(block + 0x48)
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/* ADC regular data register (ADC_DR) */
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#define ADC_DR(block) MMIO32(block + 0x4c)
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/* --- ADC Channels ------------------------------------------------------- */
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#define ADC_CHANNEL_TEMP ADC_CHANNEL16
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#define ADC_CHANNEL_VREFINT ADC_CHANNEL17
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/* --- ADC_CR1 values ------------------------------------------------------ */
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/* Note: Bits [21:20] are reserved, and must be kept at reset value. */
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/* DUALMOD[3:0]: Dual mode selection. (ADC1 only) */
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/* Legend:
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* IND: Independent mode.
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* CRSISM: Combined regular simultaneous + injected simultaneous mode.
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* CRSATM: Combined regular simultaneous + alternate trigger mode.
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* CISFIM: Combined injected simultaneous + fast interleaved mode.
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* CISSIM: Combined injected simultaneous + slow interleaved mode.
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* ISM: Injected simultaneous mode only.
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* RSM: Regular simultaneous mode only.
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* FIM: Fast interleaved mode only.
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* SIM: Slow interleaved mode only.
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* ATM: Alternate trigger mode only.
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*/
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/****************************************************************************/
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/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */
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/** @defgroup adc_cr1_dualmod ADC Mode Selection
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@ingroup adc_defines
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@{*/
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/** Independent (non-dual) mode */
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#define ADC_CR1_DUALMOD_IND (0x0 << 16)
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/** Combined regular simultaneous + injected simultaneous mode. */
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#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16)
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/** Combined regular simultaneous + alternate trigger mode. */
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#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16)
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/** Combined injected simultaneous + fast interleaved mode. */
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#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16)
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/** Combined injected simultaneous + slow interleaved mode. */
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#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16)
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/** Injected simultaneous mode only. */
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#define ADC_CR1_DUALMOD_ISM (0x5 << 16)
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/** Regular simultaneous mode only. */
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#define ADC_CR1_DUALMOD_RSM (0x6 << 16)
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/** Fast interleaved mode only. */
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#define ADC_CR1_DUALMOD_FIM (0x7 << 16)
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/** Slow interleaved mode only. */
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#define ADC_CR1_DUALMOD_SIM (0x8 << 16)
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/** Alternate trigger mode only. */
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#define ADC_CR1_DUALMOD_ATM (0x9 << 16)
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/**@}*/
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#define ADC_CR1_DUALMOD_MASK (0xF << 16)
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#define ADC_CR1_DUALMOD_SHIFT 16
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#define ADC_CR1_AWDCH_MAX 17
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/* --- ADC_CR2 values ------------------------------------------------------ */
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/* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */
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#define ADC_CR2_TSVREFE (1 << 23)
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/* SWSTART: */ /** Start conversion of regular channels. */
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#define ADC_CR2_SWSTART (1 << 22)
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/* JSWSTART: */ /** Start conversion of injected channels. */
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#define ADC_CR2_JSWSTART (1 << 21)
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/* EXTTRIG: */ /** External trigger conversion mode for regular channels. */
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#define ADC_CR2_EXTTRIG (1 << 20)
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/* EXTSEL[2:0]: External event select for regular group. */
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/* The following are only valid for ADC1 and ADC2. */
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/****************************************************************************/
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/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */
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/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2
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@ingroup adc_defines
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@{*/
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/** Timer 1 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
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/** Timer 1 Compare Output 2 */
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#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
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/** Timer 1 Compare Output 3 */
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#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
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/** Timer 2 Compare Output 2 */
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#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
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/** Timer 3 Trigger Output */
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#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
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/** Timer 4 Compare Output 4 */
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#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
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/** External Interrupt 11 */
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#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
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/** Software Trigger */
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#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
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/**@}*/
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/* The following are only valid for ADC3 */
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/****************************************************************************/
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/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */
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/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3
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@ingroup adc_defines
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@{*/
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/** Timer 2 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17)
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/** Timer 2 Compare Output 3 */
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#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17)
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/** Timer 1 Compare Output 3 */
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#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
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/** Timer 8 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17)
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/** Timer 8 Trigger Output */
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#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17)
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/** Timer 5 Compare Output 1 */
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#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17)
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/** Timer 5 Compare Output 3 */
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#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17)
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/**@}*/
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#define ADC_CR2_EXTSEL_MASK (0x7 << 17)
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#define ADC_CR2_EXTSEL_SHIFT 17
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/* Note: Bit 16 is reserved, must be kept at reset value. */
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/* JEXTTRIG: External trigger conversion mode for injected channels. */
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#define ADC_CR2_JEXTTRIG (1 << 15)
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/* JEXTSEL[2:0]: External event selection for injected group. */
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/* The following are only valid for ADC1 and ADC2. */
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/****************************************************************************/
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/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
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/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1
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and ADC2
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@ingroup adc_defines
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@{*/
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/** Timer 1 Trigger Output */
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#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
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/** Timer 1 Compare Output 4 */
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#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
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/** Timer 2 Trigger Output */
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#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
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/** Timer 2 Compare Output 1 */
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#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
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/** Timer 3 Compare Output 4 */
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#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
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/** Timer 4 Trigger Output */
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#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
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/** External Interrupt 15 */
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#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
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/** Injected Software Trigger */
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#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
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/**@}*/
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/* The following are the different meanings for ADC3 only. */
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/****************************************************************************/
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/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */
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/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3
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@ingroup adc_defines
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@{*/
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/** Timer 1 Trigger Output */
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#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
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/** Timer 1 Compare Output 4 */
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#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
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/** Timer 4 Compare Output 3 */
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#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12)
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/** Timer 8 Compare Output 2 */
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#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12)
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/** Timer 8 Compare Output 4 */
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#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
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/** Timer 5 Trigger Output */
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#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
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/** Timer 5 Compare Output 4 */
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#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
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/** Injected Software Trigger */
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#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
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/**@}*/
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#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
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#define ADC_CR2_JEXTSEL_SHIFT 12
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/* ALIGN: Data alignment. */
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#define ADC_CR2_ALIGN_RIGHT (0 << 11)
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#define ADC_CR2_ALIGN_LEFT (1 << 11)
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#define ADC_CR2_ALIGN (1 << 11)
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/* Note: Bits [10:9] are reserved and must be kept at reset value. */
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/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
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#define ADC_CR2_DMA (1 << 8)
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/* Note: Bits [7:4] are reserved and must be kept at reset value. */
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/* RSTCAL: Reset calibration. */
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#define ADC_CR2_RSTCAL (1 << 3)
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/* CAL: A/D Calibration. */
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#define ADC_CR2_CAL (1 << 2)
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/* CONT: Continous conversion. */
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#define ADC_CR2_CONT (1 << 1)
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/* ADON: A/D converter On/Off. */
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/* Note: If any other bit in this register apart from ADON is changed at the
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* same time, then conversion is not triggered. This is to prevent triggering
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* an erroneous conversion.
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* Conclusion: Must be separately written.
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*/
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#define ADC_CR2_ADON (1 << 0)
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/* --- ADC_SMPR1 values ---------------------------------------------------- */
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#define ADC_SMPR1_SMP17_LSB 21
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#define ADC_SMPR1_SMP16_LSB 18
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#define ADC_SMPR1_SMP15_LSB 15
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#define ADC_SMPR1_SMP14_LSB 12
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#define ADC_SMPR1_SMP13_LSB 9
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#define ADC_SMPR1_SMP12_LSB 6
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#define ADC_SMPR1_SMP11_LSB 3
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#define ADC_SMPR1_SMP10_LSB 0
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#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB)
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#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB)
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#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB)
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#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB)
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#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB)
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#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
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#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
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#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
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/* --- ADC_SMPR2 values ---------------------------------------------------- */
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#define ADC_SMPR2_SMP9_LSB 27
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#define ADC_SMPR2_SMP8_LSB 24
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#define ADC_SMPR2_SMP7_LSB 21
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#define ADC_SMPR2_SMP6_LSB 18
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#define ADC_SMPR2_SMP5_LSB 15
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#define ADC_SMPR2_SMP4_LSB 12
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#define ADC_SMPR2_SMP3_LSB 9
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#define ADC_SMPR2_SMP2_LSB 6
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#define ADC_SMPR2_SMP1_LSB 3
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#define ADC_SMPR2_SMP0_LSB 0
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#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB)
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#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB)
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#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB)
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#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB)
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#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB)
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#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB)
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#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB)
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#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
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#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
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#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
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/* --- ADC_SMPRx values --------------------------------------------------- */
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/****************************************************************************/
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/* ADC_SMPRG ADC Sample Time Selection for Channels */
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/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
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@ingroup adc_defines
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@{*/
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#define ADC_SMPR_SMP_1DOT5CYC 0x0
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#define ADC_SMPR_SMP_7DOT5CYC 0x1
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#define ADC_SMPR_SMP_13DOT5CYC 0x2
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#define ADC_SMPR_SMP_28DOT5CYC 0x3
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#define ADC_SMPR_SMP_41DOT5CYC 0x4
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#define ADC_SMPR_SMP_55DOT5CYC 0x5
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#define ADC_SMPR_SMP_71DOT5CYC 0x6
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#define ADC_SMPR_SMP_239DOT5CYC 0x7
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/**@}*/
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/* --- ADC_SQR1 values ----------------------------------------------------- */
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#define ADC_SQR_MAX_CHANNELS_REGULAR 16
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#define ADC_SQR1_SQ16_LSB 15
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#define ADC_SQR1_SQ15_LSB 10
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#define ADC_SQR1_SQ14_LSB 5
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#define ADC_SQR1_SQ13_LSB 0
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#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
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#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
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#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
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#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
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#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
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/* --- ADC_SQR2 values ----------------------------------------------------- */
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#define ADC_SQR2_SQ12_LSB 25
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#define ADC_SQR2_SQ11_LSB 20
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#define ADC_SQR2_SQ10_LSB 15
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#define ADC_SQR2_SQ9_LSB 10
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#define ADC_SQR2_SQ8_LSB 5
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#define ADC_SQR2_SQ7_LSB 0
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#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
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#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
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#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
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#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
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#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
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#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
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/* --- ADC_SQR3 values ----------------------------------------------------- */
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#define ADC_SQR3_SQ6_LSB 25
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#define ADC_SQR3_SQ5_LSB 20
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#define ADC_SQR3_SQ4_LSB 15
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#define ADC_SQR3_SQ3_LSB 10
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#define ADC_SQR3_SQ2_LSB 5
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#define ADC_SQR3_SQ1_LSB 0
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#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
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#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
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#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
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#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
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#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
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#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
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/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
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#define ADC_JDATA_LSB 0
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#define ADC_DATA_LSB 0
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#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */
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#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
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#define ADC_DATA_MSK (0xffff << ADC_DA)
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#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
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/* ADC1 only (dual mode) */
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void adc_start_conversion_direct(uint32_t adc);
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void adc_set_single_channel(uint32_t adc, uint8_t channel);
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void adc_set_dual_mode(uint32_t mode);
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void adc_enable_temperature_sensor(uint32_t adc);
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void adc_disable_temperature_sensor(uint32_t adc);
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void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger);
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void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger);
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void adc_reset_calibration(uint32_t adc);
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void adc_calibration(uint32_t adc);
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void adc_on(uint32_t adc)
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LIBOPENCM3_DEPRECATED("will be removed in the first release");
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END_DECLS
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#endif
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/**@}*/
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