7681597e42
When compiling with all warnings enabled, some defines can lead to warning due to missing unsigned type suffix: warning: integer overflow in expression [-Woverflow] This fix should not affected behavior at all, since calculation with such overflows lead to the same actual address when writing to that location. However, it makes the warning disappear and also defines the right data type for a memory location.
130 lines
5.2 KiB
C
130 lines
5.2 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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* Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3)
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* Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3)
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <libopencm3/cm3/memorymap.h>
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/* --- STM32F3 specific peripheral definitions ----------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE (0x40000000U)
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#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
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#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
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#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
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#define PERIPH_BASE_AHB2 (0x48000000U)
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#define PERIPH_BASE_AHB3 (0x50000000U)
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/* Register boundary addresses */
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/* APB1 */
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#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
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#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
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#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
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/* PERIPH_BASE_APB1 + 0x0C00 (0x4000 0C00 - 0x4000 0FFF): Reserved */
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#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
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#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
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/* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 27FF): Reserved */
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#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
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#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
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#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
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#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400)
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#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
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#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
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#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000)
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#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
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#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
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#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
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#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
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#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
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#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5C00)
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#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define BX_CAN_BASE (PERIPH_BASE_APB1 + 0x6400)
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/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved */
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/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
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#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
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#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
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/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 7FFF): Reserved */
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/* APB2 */
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#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)
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#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)
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#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)
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/* PERIPH_BASE_APB2 + 0x3C00 (0x4001 3C00 - 0x4001 3FFF): Reserved */
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
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#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
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#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)
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/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 2BFF): Reserved */
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#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
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#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000)
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#define COMP_BASE (PERIPH_BASE_APB2 + 0x0000)
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#define OPAMP_BASE (PERIPH_BASE_APB2 + 0x0000)
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/* AHB2 */
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#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)
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#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)
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#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)
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#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00)
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#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000)
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#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)
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/* AHB1 */
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#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)
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/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
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#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
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/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */
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#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)
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/* PERIPH_BASE_AHB1 + 0x1400 (0x4002 1400 - 0x4002 1FFF): Reserved */
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#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)
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/* PERIPH_BASE_AHB1 + 0x0800 (0x4002 0800 - 0x4002 0FFF): Reserved */
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#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000)
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#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400)
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/* AHB3 */
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#define ADC3_BASE (PERIPH_BASE_AHB3 + 0x0400)
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#define ADC4_BASE (PERIPH_BASE_AHB3 + 0x0400)
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#define ADC1_BASE (PERIPH_BASE_AHB3 + 0x0000)
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#define ADC2_BASE (PERIPH_BASE_AHB3 + 0x0000)
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/* PPIB */
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#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
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/* Device Electronic Signature */
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#define DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU)
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#define DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU)
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#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
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#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
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#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
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/* ST provided factory calibration values @ 3.3V */
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#define ST_VREFINT_CAL MMIO16(0x1FFFF7BA)
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#define ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8)
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#define ST_TSENSE_CAL2_110 MMIO16(0x1FFFF7C2)
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#endif
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