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blackmagic/lib/stm32/l0/rcc.c
Karl Palsson 3a7cbec776 stm32l/stm32f: name space standardization [BREAKING] 
As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.

    Let's not hide the fact that these variables are structs/enums.

    We are filling up the namespace badly enough, we should be prefixing as
    much as we can with the module names at least. As users we already run
    often enough in namespace colisions we don't have to make it worse.

    * CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
    * clock enums (PLL, HSI, HSE ...) prefixed with RCC_
    * scale enum of pwr module prefixed with PWR_
2015-12-14 23:26:42 +01:00

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/** @defgroup STM32L0xx-rcc-file RCC
*
* @ingroup STM32L0xx
*
* @brief <b>libopencm3 STM32L0xx Reset and Clock Control</b>
*
* @version 1.0.0
*
* @date November 2014
*
* This library supports the Reset and Clock Control System in the STM32F0xx
* series of ARM Cortex Microcontrollers by ST Microelectronics.
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2014 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/cm3/assert.h>
#include <libopencm3/stm32/rcc.h>
void rcc_osc_on(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case RCC_MSI:
RCC_CR |= RCC_CR_MSION;
break;
case RCC_HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case RCC_HSI48:
RCC_CRRCR |= RCC_CRRCR_HSI48ON;
break;
case RCC_HSI16:
RCC_CR |= RCC_CR_HSI16ON;
break;
case RCC_LSE:
RCC_CSR |= RCC_CSR_LSEON;
break;
case RCC_LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
}
void rcc_osc_off(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case RCC_MSI:
RCC_CR &= ~RCC_CR_MSION;
break;
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case RCC_HSI48:
RCC_CRRCR &= ~RCC_CRRCR_HSI48ON;
break;
case RCC_HSI16:
RCC_CR &= ~RCC_CR_HSI16ON;
break;
case RCC_LSE:
RCC_CSR &= ~RCC_CSR_LSEON;
break;
case RCC_LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
}
/* TODO easy target for shared code */
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_CSR |= RCC_CSR_LSEBYP;
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/* TODO easy target for shared code */
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_CSR &= ~RCC_CSR_LSEBYP;
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Clear the Oscillator Ready Interrupt Flag
*
* Clear the interrupt flag that was set when a clock oscillator became ready
* to use.
*
* @param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_osc_ready_int_clear(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CICR |= RCC_CICR_PLLRDYC;
break;
case RCC_HSE:
RCC_CICR |= RCC_CICR_HSERDYC;
break;
case RCC_HSI48:
RCC_CICR |= RCC_CICR_HSI48RDYC;
break;
case RCC_HSI16:
RCC_CICR |= RCC_CICR_HSI16RDYC;
break;
case RCC_MSI:
RCC_CICR |= RCC_CICR_MSIRDYC;
break;
case RCC_LSE:
RCC_CICR |= RCC_CICR_LSERDYC;
break;
case RCC_LSI:
RCC_CICR |= RCC_CICR_LSIRDYC;
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable the Oscillator Ready Interrupt
*
* @param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_osc_ready_int_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CIER |= RCC_CIER_PLLRDYIE;
break;
case RCC_HSE:
RCC_CIER |= RCC_CIER_HSERDYIE;
break;
case RCC_HSI48:
RCC_CIER |= RCC_CIER_HSI48RDYIE;
break;
case RCC_HSI16:
RCC_CIER |= RCC_CIER_HSI16RDYIE;
break;
case RCC_MSI:
RCC_CIER |= RCC_CIER_MSIRDYIE;
break;
case RCC_LSE:
RCC_CIER |= RCC_CIER_LSERDYIE;
break;
case RCC_LSI:
RCC_CIER |= RCC_CIER_LSIRDYIE;
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable the Oscillator Ready Interrupt
*
* @param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_osc_ready_int_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CIER &= ~RCC_CIER_PLLRDYIE;
break;
case RCC_HSE:
RCC_CIER &= ~RCC_CIER_HSERDYIE;
break;
case RCC_HSI48:
RCC_CIER &= ~RCC_CIER_HSI48RDYIE;
break;
case RCC_HSI16:
RCC_CIER &= ~RCC_CIER_HSI16RDYIE;
break;
case RCC_MSI:
RCC_CIER &= ~RCC_CIER_MSIRDYIE;
break;
case RCC_LSE:
RCC_CIER &= ~RCC_CIER_LSERDYIE;
break;
case RCC_LSI:
RCC_CIER &= ~RCC_CIER_LSIRDYIE;
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Read the Oscillator Ready Interrupt Flag
*
* @param[in] osc enum ::osc_t. Oscillator ID
* @returns int. Boolean value for flag set.
*/
int rcc_osc_ready_int_flag(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
break;
case RCC_HSE:
return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
break;
case RCC_HSI48:
return ((RCC_CIFR & RCC_CIFR_HSI48RDYF) != 0);
break;
case RCC_HSI16:
return ((RCC_CIFR & RCC_CIFR_HSI16RDYF) != 0);
break;
case RCC_MSI:
return ((RCC_CIFR & RCC_CIFR_MSIRDYF) != 0);
break;
case RCC_LSE:
return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
break;
case RCC_LSI:
return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
break;
}
cm3_assert_not_reached();
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Wait for Oscillator Ready.
*
* @param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_wait_for_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
break;
case RCC_HSE:
while ((RCC_CR & RCC_CR_HSERDY) == 0);
break;
case RCC_HSI16:
while ((RCC_CR & RCC_CR_HSI16RDY) == 0);
break;
case RCC_HSI48:
while ((RCC_CRRCR & RCC_CRRCR_HSI48RDY) == 0);
break;
case RCC_MSI:
while ((RCC_CR & RCC_CR_MSIRDY) == 0);
break;
case RCC_LSE:
while ((RCC_CSR & RCC_CSR_LSERDY) == 0);
break;
case RCC_LSI:
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set HSI48 clock source to the RC48 (CRS)
*/
void rcc_set_hsi48_source_rc48(void)
{
RCC_CCIPR |= RCC_CCIPR_HSI48SEL;
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set HSI48 clock source to the PLL
*/
void rcc_set_hsi48_source_pll(void)
{
RCC_CCIPR &= ~RCC_CCIPR_HSI48SEL;
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the Source for the System Clock.
*
* @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, HSI16, MSI and PLL have
* effect.
*/
void rcc_set_sysclk_source(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CFGR |= RCC_CFGR_SW_PLL;
break;
case RCC_HSE:
RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_HSE;
break;
case RCC_HSI16:
RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_HSI16;
break;
case RCC_MSI:
RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW_MSI;
break;
case RCC_HSI48:
case RCC_LSE:
case RCC_LSI:
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the PLL Multiplication Factor.
*
* @note This only has effect when the PLL is disabled.
*
* @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
*/
void rcc_set_pll_multiplier(uint32_t factor)
{
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
RCC_CFGR = reg | (factor << RCC_CFGR_PLLMUL_SHIFT);
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the PLL Division Factor.
*
* @note This only has effect when the PLL is disabled.
*
* @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pdf
*/
void rcc_set_pll_divider(uint32_t factor)
{
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT);
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the APB1 Prescale Factor.
*
* @note The APB1 clock frequency must not exceed 32MHz.
*
* @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre
*/
void rcc_set_ppre1(uint32_t ppre)
{
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE1_SHIFT);
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the APB2 Prescale Factor.
*
* @note The APB2 clock frequency must not exceed 32MHz.
*
* @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb2pre
*/
void rcc_set_ppre2(uint32_t ppre)
{
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE2_SHIFT);
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the AHB Prescale Factor.
*
* @param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
*/
void rcc_set_hpre(uint32_t hpre)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT);
}
/**@}*/
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