7957cffaa3
Add an abstraction layer to handle the clock control for the run time clock on LM4F (RCC). Sleep and deep-sleep clock configuration is not handled. Complete documentation for the clock control API is included in doxygen-style comments, and is included in [doc]. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Conflicts: lib/lm4f/Makefile
727 lines
24 KiB
C
727 lines
24 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LM4F_SYSTEMCONTROL_H
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#define LM4F_SYSTEMCONTROL_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lm4f/memorymap.h>
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#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000)
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#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004)
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#define SYSCTL_PBORCTL MMIO32(SYSCTL_BASE + 0x030)
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#define SYSCTL_LDORCTL MMIO32(SYSCTL_BASE + 0x034)
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#define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050)
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#define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054)
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#define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058)
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#define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C)
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#define SYSCTL_RCC MMIO32(SYSCTL_BASE + 0x060)
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#define SYSCTL_PLLCFG MMIO32(SYSCTL_BASE + 0x064)
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#define SYSCTL_GPIOHBCTL MMIO32(SYSCTL_BASE + 0x06C)
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#define SYSCTL_RCC2 MMIO32(SYSCTL_BASE + 0x070)
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#define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C)
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#define SYSCTL_DSLPCLKCFG MMIO32(SYSCTL_BASE + 0x144)
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#define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C)
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#define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150)
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#define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154)
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#define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160)
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#define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164)
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#define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168)
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/* Peripheral present */
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#define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300)
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#define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304)
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#define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308)
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#define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C)
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#define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314)
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#define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318)
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#define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C)
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#define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320)
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#define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328)
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#define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334)
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#define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338)
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#define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C)
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#define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340)
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#define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344)
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#define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358)
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#define SYSCTL_PPWTIMER MMIO32(SYSCTL_BASE + 0x35C)
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/* Peripheral software reset */
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#define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500)
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#define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504)
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#define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508)
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#define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C)
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#define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514)
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#define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518)
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#define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C)
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#define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520)
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#define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528)
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#define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534)
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#define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538)
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#define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C)
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#define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540)
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#define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544)
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#define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558)
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#define SYSCTL_SRWTIMER MMIO32(SYSCTL_BASE + 0x55C)
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/* Peripheral run mode clock gating control */
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#define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600)
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#define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604)
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#define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608)
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#define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C)
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#define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614)
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#define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618)
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#define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C)
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#define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620)
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#define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628)
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#define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634)
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#define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638)
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#define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C)
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#define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640)
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#define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644)
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#define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658)
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#define SYSCTL_RCGCWTIMER MMIO32(SYSCTL_BASE + 0x65C)
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/* Peripheral sleep mode clock gating control */
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#define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700)
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#define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704)
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#define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708)
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#define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C)
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#define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714)
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#define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718)
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#define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C)
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#define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720)
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#define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728)
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#define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734)
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#define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738)
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#define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C)
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#define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740)
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#define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744)
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#define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758)
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#define SYSCTL_SCGCWTIMER MMIO32(SYSCTL_BASE + 0x75C)
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/* Peripheral deep-sleep mode clock gating control */
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#define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800)
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#define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804)
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#define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808)
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#define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C)
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#define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814)
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#define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818)
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#define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C)
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#define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820)
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#define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828)
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#define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834)
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#define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838)
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#define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C)
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#define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840)
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#define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844)
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#define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858)
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#define SYSCTL_DCGCWTIMER MMIO32(SYSCTL_BASE + 0x85C)
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/* Peripheral ready */
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#define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00)
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#define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04)
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#define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08)
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#define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C)
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#define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14)
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#define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18)
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#define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C)
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#define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20)
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#define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28)
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#define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34)
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#define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38)
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#define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C)
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#define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40)
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#define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44)
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#define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58)
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#define SYSCTL_PRWTIMER MMIO32(SYSCTL_BASE + 0xA5C)
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/* =============================================================================
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* System Control Legacy Registers
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* ---------------------------------------------------------------------------*/
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#ifdef LM4F_LEGACY_SYSCTL
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#define SYSCTL_DC0 MMIO32(SYSCTL_BASE + 0x008)
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#define SYSCTL_DC1 MMIO32(SYSCTL_BASE + 0x010)
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#define SYSCTL_DC2 MMIO32(SYSCTL_BASE + 0x014)
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#define SYSCTL_DC3 MMIO32(SYSCTL_BASE + 0x018)
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#define SYSCTL_DC4 MMIO32(SYSCTL_BASE + 0x01C)
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#define SYSCTL_DC5 MMIO32(SYSCTL_BASE + 0x020)
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#define SYSCTL_DC6 MMIO32(SYSCTL_BASE + 0x024)
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#define SYSCTL_DC7 MMIO32(SYSCTL_BASE + 0x028)
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#define SYSCTL_DC8 MMIO32(SYSCTL_BASE + 0x02C)
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#define SYSCTL_SRCR0 MMIO32(SYSCTL_BASE + 0x040)
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#define SYSCTL_SRCR1 MMIO32(SYSCTL_BASE + 0x044)
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#define SYSCTL_SRCR2 MMIO32(SYSCTL_BASE + 0x048)
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#define SYSCTL_RCGC0 MMIO32(SYSCTL_BASE + 0x100)
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#define SYSCTL_RCGC1 MMIO32(SYSCTL_BASE + 0x104)
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#define SYSCTL_RCGC2 MMIO32(SYSCTL_BASE + 0x108)
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#define SYSCTL_SCGC0 MMIO32(SYSCTL_BASE + 0x110)
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#define SYSCTL_SCGC1 MMIO32(SYSCTL_BASE + 0x114)
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#define SYSCTL_SCGC2 MMIO32(SYSCTL_BASE + 0x118)
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#define SYSCTL_DCGC0 MMIO32(SYSCTL_BASE + 0x120)
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#define SYSCTL_DCGC1 MMIO32(SYSCTL_BASE + 0x124)
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#define SYSCTL_DCGC2 MMIO32(SYSCTL_BASE + 0x128)
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#define SYSCTL_DC9 MMIO32(SYSCTL_BASE + 0x190)
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#define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0)
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#endif /* LM4F_LEGACY_SYSCTL */
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/* =============================================================================
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* SYSCTL_DID0 values
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* ---------------------------------------------------------------------------*/
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/** DID0 version */
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#define SYSCTL_DID0_VER_MASK (7 << 28)
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/** Device class */
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#define SYSCTL_DID0_CLASS_MASK (0xFF << 16)
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/** Major revision */
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#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8)
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/** Minor revision */
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#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8)
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/* =============================================================================
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* SYSCTL_DID1 values
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* ---------------------------------------------------------------------------*/
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/** DID1 version */
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#define SYSCTL_DID1_VER_MASK (0xF << 28)
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/** Family */
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#define SYSCTL_DID1_FAM_MASK (0xF << 24)
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/** Part number */
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#define SYSCTL_DID1_PARTNO_MASK (0xFF << 16)
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/** Pin count */
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#define SYSCTL_DID1_PINCOUNT_MASK (0x7 << 13)
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#define SYSCTL_DID1_PINCOUNT_28P (0x0 << 13)
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#define SYSCTL_DID1_PINCOUNT_48P (0x1 << 13)
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#define SYSCTL_DID1_PINCOUNT_100P (0x2 << 13)
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#define SYSCTL_DID1_PINCOUNT_64P (0x3 << 13)
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#define SYSCTL_DID1_PINCOUNT_144P (0x4 << 13)
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#define SYSCTL_DID1_PINCOUNT_157P (0x5 << 13)
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/** Temperature range */
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#define SYSCTL_DID1_TEMP_MASK (0x7 << 5)
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#define SYSCTL_DID1_TEMP_0_70 (0x0 << 5)
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#define SYSCTL_DID1_TEMP_M40_85 (0x1 << 5)
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#define SYSCTL_DID1_TEMP_M40_105 (0x2 << 5)
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/** Package */
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#define SYSCTL_DID1_PKG_MASK (0x3 << 5)
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#define SYSCTL_DID1_PKG_SOIC (0x0 << 5)
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#define SYSCTL_DID1_PKG_LQFP (0x1 << 5)
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#define SYSCTL_DID1_PKG_BGA (0x2 << 5)
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/** ROHS compliance */
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#define SYSCTL_DID1_ROHS (1 << 2)
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/** Qualification status */
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#define SYSCTL_DID1_QUAL_MASK (3 << 0)
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/* =============================================================================
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* SYSCTL_PBORCTL values
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* ---------------------------------------------------------------------------*/
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/** BOR interrupt or reset */
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#define SYSCTL_PBORCTL_BORIOR (1 << 1)
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/* =============================================================================
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* SYSCTL_RIS values
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* ---------------------------------------------------------------------------*/
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/** MOSC Power Up Raw Interrupt Status */
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#define SYSCTL_RIS_MOSCPUPRIS (1 << 8)
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/** USB PLL Lock Raw Interrupt Status */
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#define SYSCTL_RIS_USBPLLLRIS (1 << 7)
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/** PLL Lock Raw Interrupt Status */
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#define SYSCTL_RIS_PLLLRIS (1 << 6)
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/** Main Oscillator Failure Raw Interrupt Status */
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#define SYSCTL_RIS_MOFRIS (1 << 3)
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/** Brown-Out Reset Raw Interrupt Status */
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#define SYSCTL_RIS_BORRIS (1 << 1)
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/* =============================================================================
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* SYSCTL_IMC values
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* ---------------------------------------------------------------------------*/
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/** MOSC Power Up Raw Interrupt Status */
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#define SYSCTL_IMC_MOSCPUPIM (1 << 8)
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/** USB PLL Lock Raw Interrupt Status */
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#define SYSCTL_IMC_USBPLLLIM (1 << 7)
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/** PLL Lock Raw Interrupt Status */
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#define SYSCTL_IMC_PLLLIM (1 << 6)
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/** Main Oscillator Failure Raw Interrupt Status */
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#define SYSCTL_IMC_MOFIM (1 << 3)
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/** Brown-Out Reset Raw Interrupt Status */
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#define SYSCTL_IMC_BORIM (1 << 1)
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/* =============================================================================
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* SYSCTL_MISC values
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* ---------------------------------------------------------------------------*/
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/** MOSC Power Up Raw Interrupt Status */
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#define SYSCTL_MISC_MOSCPUPMIS (1 << 8)
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/** USB PLL Lock Raw Interrupt Status */
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#define SYSCTL_MISC_USBPLLLMIS (1 << 7)
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/** PLL Lock Raw Interrupt Status */
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#define SYSCTL_MISC_PLLLMIS (1 << 6)
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/** Main Oscillator Failure Raw Interrupt Status */
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#define SYSCTL_MISC_MOFMIS (1 << 3)
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/** Brown-Out Reset Raw Interrupt Status */
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#define SYSCTL_MISC_BORMIS (1 << 1)
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/* =============================================================================
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* SYSCTL_RESC values
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* ---------------------------------------------------------------------------*/
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/** MOSC Failure Reset */
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#define SYSCTL_RESC_MOSCFAIL (1 << 18)
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/** Watchdog Timer 1 Reset */
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#define SYSCTL_RESC_WDT1 (1 << 5)
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/** Software Reset */
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#define SYSCTL_RESC_SW (1 << 4)
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/** Watchdog Timer 0 Reset */
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#define SYSCTL_RESC_WDT0 (1 << 3)
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/** Brown-Out Reset */
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#define SYSCTL_RESC_BOR (1 << 2)
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/** Power-On Reset */
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#define SYSCTL_RESC_POR (1 << 1)
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/** External Reset */
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#define SYSCTL_RESC_EXT (1 << 0)
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/* =============================================================================
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* SYSCTL_RCC values
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* ---------------------------------------------------------------------------*/
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/** Auto Clock Gating */
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#define SYSCTL_RCC_ACG (1 << 27)
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/** System Clock Divisor */
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#define SYSCTL_RCC_SYSDIV_MASK (0xF << 23)
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/** Enable System Clock Divider */
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#define SYSCTL_RCC_USESYSDIV (1 << 22)
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/** Enable PWM Clock Divisor */
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#define SYSCTL_RCC_USEPWMDIV (1 << 20)
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/** PWM Unit Clock Divisor */
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#define SYSCTL_RCC_PWMDIV_MASK (0xF << 17)
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#define SYSCTL_RCC_PWMDIV_2 (0x0 << 17)
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#define SYSCTL_RCC_PWMDIV_4 (0x1 << 17)
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#define SYSCTL_RCC_PWMDIV_8 (0x2 << 17)
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#define SYSCTL_RCC_PWMDIV_16 (0x3 << 17)
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#define SYSCTL_RCC_PWMDIV_32 (0x4 << 17)
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#define SYSCTL_RCC_PWMDIV_64 (0x5 << 17)
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/** PLL Power Down */
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#define SYSCTL_RCC_PWRDN (1 << 13)
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/** PLL Bypass */
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#define SYSCTL_RCC_BYPASS (1 << 11)
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/** Crystal Value */
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#define SYSCTL_RCC_XTAL_MASK (0x1F << 6)
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#define SYSCTL_RCC_XTAL_4M (0x06 << 6)
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#define SYSCTL_RCC_XTAL_4M_096 (0x07 << 6)
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#define SYSCTL_RCC_XTAL_4M_9152 (0x08 << 6)
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#define SYSCTL_RCC_XTAL_5M (0x09 << 6)
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#define SYSCTL_RCC_XTAL_5M_12 (0x0A << 6)
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#define SYSCTL_RCC_XTAL_6M (0x0B << 6)
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#define SYSCTL_RCC_XTAL_6M_144 (0x0C << 6)
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#define SYSCTL_RCC_XTAL_7M_3728 (0x0D << 6)
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#define SYSCTL_RCC_XTAL_8M (0x0E << 6)
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#define SYSCTL_RCC_XTAL_8M_192 (0x0F << 6)
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#define SYSCTL_RCC_XTAL_10M (0x10 << 6)
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#define SYSCTL_RCC_XTAL_12M (0x11 << 6)
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#define SYSCTL_RCC_XTAL_12M_288 (0x12 << 6)
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#define SYSCTL_RCC_XTAL_13M_56 (0x13 << 6)
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#define SYSCTL_RCC_XTAL_14M_31818 (0x14 << 6)
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#define SYSCTL_RCC_XTAL_16M (0x15 << 6)
|
|
#define SYSCTL_RCC_XTAL_16M_384 (0x16 << 6)
|
|
#define SYSCTL_RCC_XTAL_18M (0x17 << 6)
|
|
#define SYSCTL_RCC_XTAL_20M (0x18 << 6)
|
|
#define SYSCTL_RCC_XTAL_24M (0x19 << 6)
|
|
#define SYSCTL_RCC_XTAL_25M (0x1A << 6)
|
|
/** Oscillator Source */
|
|
#define SYSCTL_RCC_OSCSRC_MASK (0x3 << 4)
|
|
#define SYSCTL_RCC_OSCSRC_MOSC (0x0 << 4)
|
|
#define SYSCTL_RCC_OSCSRC_PIOSC (0x1 << 4)
|
|
#define SYSCTL_RCC_OSCSRC_PIOSC_D4 (0x2 << 4)
|
|
#define SYSCTL_RCC_OSCSRC_30K (0x3 << 4)
|
|
/** Precision Internal Oscillator Disable */
|
|
#define SYSCTL_RCC_IOSCDIS (1 << 1)
|
|
/** Main Oscillator Disable */
|
|
#define SYSCTL_RCC_MOSCDIS (1 << 0)
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_GPIOHBCTL values
|
|
* ---------------------------------------------------------------------------*/
|
|
#define SYSCTL_GPIOHBCTL_PORTQ (1 << 14)
|
|
#define SYSCTL_GPIOHBCTL_PORTP (1 << 13)
|
|
#define SYSCTL_GPIOHBCTL_PORTN (1 << 12)
|
|
#define SYSCTL_GPIOHBCTL_PORTM (1 << 11)
|
|
#define SYSCTL_GPIOHBCTL_PORTL (1 << 10)
|
|
#define SYSCTL_GPIOHBCTL_PORTK (1 << 9)
|
|
#define SYSCTL_GPIOHBCTL_PORTJ (1 << 8)
|
|
#define SYSCTL_GPIOHBCTL_PORTH (1 << 7)
|
|
#define SYSCTL_GPIOHBCTL_PORTG (1 << 6)
|
|
#define SYSCTL_GPIOHBCTL_PORTF (1 << 5)
|
|
#define SYSCTL_GPIOHBCTL_PORTE (1 << 4)
|
|
#define SYSCTL_GPIOHBCTL_PORTD (1 << 3)
|
|
#define SYSCTL_GPIOHBCTL_PORTC (1 << 2)
|
|
#define SYSCTL_GPIOHBCTL_PORTB (1 << 1)
|
|
#define SYSCTL_GPIOHBCTL_PORTA (1 << 0)
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_RCC2 values
|
|
* ---------------------------------------------------------------------------*/
|
|
/** RCC2 overides RCC */
|
|
#define SYSCTL_RCC2_USERCC2 (1 << 31)
|
|
/** Divide PLL as 400 MHz vs. 200 MHz */
|
|
#define SYSCTL_RCC2_DIV400 (1 << 30)
|
|
/** Auto Clock Gating */
|
|
#define SYSCTL_RCC2_ACG (1 << 27)
|
|
/** System Clock Divisor 2 */
|
|
#define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23)
|
|
/** Additional LSB for SYSDIV2 */
|
|
#define SYSCTL_RCC2_SYSDIV2LSB (1 << 22)
|
|
/** System clock divisor mask when RCC2_DIV400 is set */
|
|
#define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22)
|
|
/** Power-Down USB PLL */
|
|
#define SYSCTL_RCC2_USBPWRDN (1 << 14)
|
|
/** PLL Power Down 2 */
|
|
#define SYSCTL_RCC2_PWRDN2 (1 << 13)
|
|
/** PLL Bypass 2 */
|
|
#define SYSCTL_RCC2_BYPASS2 (1 << 11)
|
|
/** Oscillator Source 2 */
|
|
#define SYSCTL_RCC2_OSCSRC2_MASK (0x7 << 4)
|
|
#define SYSCTL_RCC2_OSCSRC2_MOSC (0x0 << 4)
|
|
#define SYSCTL_RCC2_OSCSRC2_PIOSC (0x1 << 4)
|
|
#define SYSCTL_RCC2_OSCSRC2_PIOSC_D4 (0x2 << 4)
|
|
#define SYSCTL_RCC2_OSCSRC2_30K (0x3 << 4)
|
|
#define SYSCTL_RCC2_OSCSRC2_32K768 (0x7 << 4)
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_MOSCCTL values
|
|
* ---------------------------------------------------------------------------*/
|
|
/** No Crystal Connected */
|
|
#define SYSCTL_MOSCCTL_NOXTAL (1 << 2)
|
|
/** MOSC Failure Action */
|
|
#define SYSCTL_MOSCCTL_MOSCIM (1 << 1)
|
|
/** Clock Validation for MOSC */
|
|
#define SYSCTL_MOSCCTL_CVAL (1 << 0)
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_DSLPCLKCFG values
|
|
* ---------------------------------------------------------------------------*/
|
|
/*TODO*/
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_SYSPROP values
|
|
* ---------------------------------------------------------------------------*/
|
|
/** FPU present */
|
|
#define SYSCTL_SYSPROP_FPU (1 << 0)
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_PIOSCCAL values
|
|
* ---------------------------------------------------------------------------*/
|
|
/** Use User Trim Value */
|
|
#define SYSCTL_PIOSCCAL_UTEN (1 << 31)
|
|
/** Start calibration */
|
|
#define SYSCTL_PIOSCCAL_CAL (1 << 9)
|
|
/** Update trim */
|
|
#define SYSCTL_PIOSCCAL_UPDATE (1 << 8)
|
|
/** User Trim Value */
|
|
#define SYSCTL_PIOSCCAL_UT_MASK (0x7F << 0)
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_PIOSCSTAT values
|
|
* ---------------------------------------------------------------------------*/
|
|
/** Default Trim Value */
|
|
#define SYSCTL_PIOSCSTAT_DT_MASK (0x7F << 16)
|
|
/** Calibration result */
|
|
#define SYSCTL_PIOSCSTAT_RESULT_MASK (0x3 << 8)
|
|
/** Calibration Trim Value */
|
|
#define SYSCTL_PIOSCSTAT_CT_MASK (0x7F << 0)
|
|
/* =============================================================================
|
|
* SYSCTL_PLLFREQ0 values
|
|
* ---------------------------------------------------------------------------*/
|
|
/** PLL M fractional value */
|
|
#define SYSCTL_PLLFREQ0_MFRAC_MASK (0x3FF << 10)
|
|
/** PLL M integer value */
|
|
#define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF << 0)
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_PLLFREQ1 values
|
|
* ---------------------------------------------------------------------------*/
|
|
/** PLL Q value */
|
|
#define SYSCTL_PLLFREQ1_Q_MASK (0x1F << 8)
|
|
/** PLL N value */
|
|
#define SYSCTL_PLLFREQ1_N_MASK (0x1F << 0)
|
|
|
|
/* =============================================================================
|
|
* SYSCTL_PLLSTAT values
|
|
* ---------------------------------------------------------------------------*/
|
|
/** PLL lock */
|
|
#define SYSCTL_PLLSTAT_LOCK (1 << 0)
|
|
|
|
/* =============================================================================
|
|
* Convenience definitions for a readable API
|
|
* ---------------------------------------------------------------------------*/
|
|
/**
|
|
* \brief Clock enable definitions
|
|
*
|
|
* The definitions are specified in the form
|
|
* 31:5 register offset from SYSCTL_BASE for the clock register
|
|
* 4:0 bit offset for the given peripheral
|
|
*
|
|
* The names have the form [clock_type]_[periph_type]_[periph_number]
|
|
* Where clock_type is
|
|
* RCC for run clock
|
|
* SCC for sleep clock
|
|
* DCC for deep-sleep clock
|
|
*/
|
|
typedef enum {
|
|
/*
|
|
* Run clock control
|
|
*/
|
|
RCC_WD0 = ((u32)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
|
|
RCC_WD1,
|
|
|
|
RCC_TIMER0 = ((u32)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
|
|
RCC_TIMER1,
|
|
RCC_TIMER2,
|
|
RCC_TIMER3,
|
|
RCC_TIMER4,
|
|
RCC_TIMER5,
|
|
|
|
RCC_GPIOA = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
|
|
RCC_GPIOB,
|
|
RCC_GPIOC,
|
|
RCC_GPIOD,
|
|
RCC_GPIOE,
|
|
RCC_GPIOF,
|
|
RCC_GPIOG,
|
|
RCC_GPIOH,
|
|
RCC_GPIOJ,
|
|
RCC_GPIOK,
|
|
RCC_GPIOL,
|
|
RCC_GPIOM,
|
|
RCC_GPION,
|
|
RCC_GPIOP,
|
|
RCC_GPIOQ,
|
|
|
|
RCC_DMA = ((u32)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
|
|
|
|
RCC_HIB = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
|
|
|
|
RCC_UART0 = ((u32)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
|
|
RCC_UART1,
|
|
RCC_UART2,
|
|
RCC_UART3,
|
|
RCC_UART4,
|
|
RCC_UART5,
|
|
RCC_UART6,
|
|
RCC_UART7,
|
|
|
|
RCC_SSI0 = ((u32)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
|
|
RCC_SSI1,
|
|
RCC_SSI2,
|
|
RCC_SSI3,
|
|
|
|
RCC_I2C0 = ((u32)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
|
|
RCC_I2C1,
|
|
RCC_I2C2,
|
|
RCC_I2C3,
|
|
RCC_I2C4,
|
|
RCC_I2C5,
|
|
|
|
RCC_USB0 = ((u32)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
|
|
|
|
RCC_CAN0 = ((u32)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
|
|
RCC_CAN1,
|
|
|
|
RCC_ADC0 = ((u32)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
|
|
RCC_ADC1,
|
|
|
|
RCC_ACMP0 = ((u32)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
|
|
|
|
RCC_PWM0 = ((u32)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
|
|
RCC_PWM1,
|
|
|
|
RCC_QEI0 = ((u32)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
|
|
RCC_QEI1,
|
|
|
|
RCC_EEPROM0 = ((u32)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
|
|
|
|
RCC_WTIMER0 = ((u32)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
|
|
RCC_WTIMER1,
|
|
RCC_WTIMER2,
|
|
RCC_WTIMER3,
|
|
RCC_WTIMER4,
|
|
RCC_WTIMER5,
|
|
|
|
|
|
/*
|
|
* Sleep clock control
|
|
*/
|
|
SCC_WD0 = ((u32)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
|
|
SCC_WD1,
|
|
|
|
SCC_TIMER0 = ((u32)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
|
|
SCC_TIMER1,
|
|
SCC_TIMER2,
|
|
SCC_TIMER3,
|
|
SCC_TIMER4,
|
|
SCC_TIMER5,
|
|
|
|
SCC_GPIOA = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
|
|
SCC_GPIOB,
|
|
SCC_GPIOC,
|
|
SCC_GPIOD,
|
|
SCC_GPIOE,
|
|
SCC_GPIOF,
|
|
SCC_GPIOG,
|
|
SCC_GPIOH,
|
|
SCC_GPIOJ,
|
|
SCC_GPIOK,
|
|
SCC_GPIOL,
|
|
SCC_GPIOM,
|
|
SCC_GPION,
|
|
SCC_GPIOP,
|
|
SCC_GPIOQ,
|
|
|
|
SCC_DMA = ((u32)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
|
|
|
|
SCC_HIB = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
|
|
|
|
SCC_UART0 = ((u32)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
|
|
SCC_UART1,
|
|
SCC_UART2,
|
|
SCC_UART3,
|
|
SCC_UART4,
|
|
SCC_UART5,
|
|
SCC_UART6,
|
|
SCC_UART7,
|
|
|
|
SCC_SSI0 = ((u32)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
|
|
SCC_SSI1,
|
|
SCC_SSI2,
|
|
SCC_SSI3,
|
|
|
|
SCC_I2C0 = ((u32)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
|
|
SCC_I2C1,
|
|
SCC_I2C2,
|
|
SCC_I2C3,
|
|
SCC_I2C4,
|
|
SCC_I2C5,
|
|
|
|
SCC_USB0 = ((u32)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
|
|
|
|
SCC_CAN0 = ((u32)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
|
|
SCC_CAN1,
|
|
|
|
SCC_ADC0 = ((u32)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
|
|
SCC_ADC1,
|
|
|
|
SCC_ACMP0 = ((u32)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
|
|
|
|
SCC_PWM0 = ((u32)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
|
|
SCC_PWM1,
|
|
|
|
SCC_QEI0 = ((u32)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
|
|
SCC_QEI1,
|
|
|
|
SCC_EEPROM0 = ((u32)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
|
|
|
|
SCC_WTIMER0 = ((u32)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
|
|
SCC_WTIMER1,
|
|
SCC_WTIMER2,
|
|
SCC_WTIMER3,
|
|
SCC_WTIMER4,
|
|
SCC_WTIMER5,
|
|
|
|
/*
|
|
* Deep-sleep clock control
|
|
*/
|
|
DCC_WD0 = ((u32)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
|
|
DCC_WD1,
|
|
|
|
DCC_TIMER0 = ((u32)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
|
|
DCC_TIMER1,
|
|
DCC_TIMER2,
|
|
DCC_TIMER3,
|
|
DCC_TIMER4,
|
|
DCC_TIMER5,
|
|
|
|
DCC_GPIOA = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
|
|
DCC_GPIOB,
|
|
DCC_GPIOC,
|
|
DCC_GPIOD,
|
|
DCC_GPIOE,
|
|
DCC_GPIOF,
|
|
DCC_GPIOG,
|
|
DCC_GPIOH,
|
|
DCC_GPIOJ,
|
|
DCC_GPIOK,
|
|
DCC_GPIOL,
|
|
DCC_GPIOM,
|
|
DCC_GPION,
|
|
DCC_GPIOP,
|
|
DCC_GPIOQ,
|
|
|
|
DCC_DMA = ((u32)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
|
|
|
|
DCC_HIB = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
|
|
|
|
DCC_UART0 = ((u32)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
|
|
DCC_UART1,
|
|
DCC_UART2,
|
|
DCC_UART3,
|
|
DCC_UART4,
|
|
DCC_UART5,
|
|
DCC_UART6,
|
|
DCC_UART7,
|
|
|
|
DCC_SSI0 = ((u32)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
|
|
DCC_SSI1,
|
|
DCC_SSI2,
|
|
DCC_SSI3,
|
|
|
|
DCC_I2C0 = ((u32)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
|
|
DCC_I2C1,
|
|
DCC_I2C2,
|
|
DCC_I2C3,
|
|
DCC_I2C4,
|
|
DCC_I2C5,
|
|
|
|
DCC_USB0 = ((u32)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
|
|
|
|
DCC_CAN0 = ((u32)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
|
|
DCC_CAN1,
|
|
|
|
DCC_ADC0 = ((u32)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
|
|
DCC_ADC1,
|
|
|
|
DCC_ACMP0 = ((u32)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
|
|
|
|
DCC_PWM0 = ((u32)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
|
|
DCC_PWM1,
|
|
|
|
DCC_QEI0 = ((u32)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
|
|
DCC_QEI1,
|
|
|
|
DCC_EEPROM0 = ((u32)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
|
|
|
|
DCC_WTIMER0 = ((u32)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
|
|
DCC_WTIMER1,
|
|
DCC_WTIMER2,
|
|
DCC_WTIMER3,
|
|
DCC_WTIMER4,
|
|
DCC_WTIMER5,
|
|
|
|
} clken_t;
|
|
|
|
/* =============================================================================
|
|
* Function prototypes
|
|
* ---------------------------------------------------------------------------*/
|
|
BEGIN_DECLS
|
|
|
|
void periph_clock_enable(clken_t periph);
|
|
void periph_clock_disable(clken_t periph);
|
|
|
|
END_DECLS
|
|
|
|
#endif /* LM4F_SYSTEMCONTROL_H */
|
|
|
|
|
|
|