280 lines
8.9 KiB
C
280 lines
8.9 KiB
C
/** @defgroup flash_defines FLASH Defines
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*
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* @ingroup STM32G0xx_defines
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*
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* @brief <b>Defined Constants and Types for the STM32G0xx Flash Control</b>
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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* */
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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#include <libopencm3/stm32/common/flash_common_all.h>
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/** @defgroup flash_registers FLASH Registers
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@{*/
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#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
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#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
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#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0c)
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#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
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#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
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#define FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
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#define FLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
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#define FLASH_PCROP1ASR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24)
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#define FLASH_PCROP1AER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28)
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#define FLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2c)
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#define FLASH_WRP1BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x30)
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#define FLASH_PCROP1BSR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x34)
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#define FLASH_PCROP1BER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x38)
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#define FLASH_SECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80)
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/**@}*/
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/** @defgroup flash_acr ACR Access control register
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@{*/
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/** FLASH_ACR_DBG_SWEN Debug access software enable **/
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#define FLASH_ACR_DBG_SWEN (1 << 18)
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/** FLASH_ACR_EMPTY Flash User area empty **/
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#define FLASH_ACR_EMPTY (1 << 16)
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/** FLASH_ACR_ICRST Instruction cache reset **/
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#define FLASH_ACR_ICRST (1 << 11)
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/** FLASH_ACR_ICEN Instruction cache enable **/
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#define FLASH_ACR_ICEN (1 << 9)
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/** FLASH_ACR_PRFTEN Prefetch enable **/
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#define FLASH_ACR_PRFTEN (1 << 8)
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#define FLASH_ACR_LATENCY_SHIFT 0
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#define FLASH_ACR_LATENCY_MASK 0x7
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/** @defgroup flash_latency FLASH Wait States
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* @brief Flash memory access latency. flash HCLK max freq for 0ws is 24mhz (range 1 voltage) / 8mhz (range 0), 48mhz/16mhz for 1ws and 64mhz for 2ws.
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@{*/
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#define FLASH_ACR_LATENCY_0WS 0x00
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#define FLASH_ACR_LATENCY_1WS 0x01
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#define FLASH_ACR_LATENCY_2WS 0x02
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/**@}*/
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/**@}*/
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/** @defgroup flash_keyr KEYR Flash key register
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@{*/
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/** FLASH_KEYR_KEY1 Flash key 1 **/
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#define FLASH_KEYR_KEY1 ((uint32_t)0x08192a3b)
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/** FLASH_KEYR_KEY2 Flash key 2 **/
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#define FLASH_KEYR_KEY2 ((uint32_t)0x4c5d6e7f)
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/**@}*/
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/** @defgroup flash_optkeyr OPTKEYR Option byte key register
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@{*/
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/** FLASH_OPTKEYR_KEY1 Option key 1 **/
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#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1
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/** FLASH_OPTKEYR_KEY2 Option key 2 **/
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#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2
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/**@}*/
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/** @defgroup flash_sr SR Status register
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@{*/
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/** FLASH_SR_CFGBSY Programming or erase configuration busy. **/
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#define FLASH_SR_CFGBSY (1 << 18)
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/** FLASH_SR_BSY Busy **/
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#define FLASH_SR_BSY (1 << 16)
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/** FLASH_SR_OPTVERR Option and Engineering bits loading validity error **/
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#define FLASH_SR_OPTVERR (1 << 15)
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/** FLASH_SR_RDERR PCROP read error **/
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#define FLASH_SR_RDERR (1 << 14)
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/** FLASH_SR_FASTERR Fast programming error **/
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#define FLASH_SR_FASTERR (1 << 9)
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/** FLASH_SR_MISERR Fast programming data miss error **/
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#define FLASH_SR_MISERR (1 << 8)
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/** FLASH_SR_PGSERR Programming sequence error **/
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#define FLASH_SR_PGSERR (1 << 7)
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/** FLASH_SR_SIZERR Size error **/
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#define FLASH_SR_SIZERR (1 << 6)
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/** FLASH_SR_PGAERR Programming alignment error **/
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#define FLASH_SR_PGAERR (1 << 5)
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/** FLASH_SR_WRPERR Write protected error **/
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#define FLASH_SR_WRPERR (1 << 4)
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/** FLASH_SR_PROGERR Programming error **/
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#define FLASH_SR_PROGERR (1 << 3)
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/** FLASH_SR_OPERR Operation error **/
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#define FLASH_SR_OPERR (1 << 1)
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/** FLASH_SR_EOP End of operation **/
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#define FLASH_SR_EOP (1 << 0)
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/**@}*/
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/** @defgroup flash_cr CR Flash control register
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@{*/
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/** FLASH_CR_LOCK FLASH_CR Lock **/
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#define FLASH_CR_LOCK (1 << 31)
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/** FLASH_CR_OPTLOCK Options Lock **/
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#define FLASH_CR_OPTLOCK (1 << 30)
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/** FLASH_CR_SEC_PROT Securable memory area protection enable **/
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#define FLASH_CR_SEC_PROT (1 << 28)
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/** FLASH_CR_OBL_LAUNCH Force the option byte loading **/
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#define FLASH_CR_OBL_LAUNCH (1 << 27)
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/** FLASH_CR_RDERRIE PCROP read error interrupt enable **/
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#define FLASH_CR_RDERRIE (1 << 26)
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/** FLASH_CR_ERRIE Error interrupt enable **/
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#define FLASH_CR_ERRIE (1 << 25)
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/** FLASH_CR_EOPIE End of operation interrupt enable **/
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#define FLASH_CR_EOPIE (1 << 24)
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/** FLASH_CR_FSTPG Fast programming **/
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#define FLASH_CR_FSTPG (1 << 18)
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/** FLASH_CR_OPTSTRT Options modification start **/
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#define FLASH_CR_OPTSTRT (1 << 17)
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/** FLASH_CR_STRT Start **/
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_PNB_SHIFT 3
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#define FLASH_CR_PNB_MASK 0x3f
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/** FLASH_CR_MER Mass erase **/
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#define FLASH_CR_MER (1 << 2)
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/** FLASH_CR_PER Page erase **/
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#define FLASH_CR_PER (1 << 1)
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/** FLASH_CR_PG Programming **/
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#define FLASH_CR_PG (1 << 0)
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/**@}*/
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/** @defgroup flash_eccr ECCR Flash ECC register
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@{*/
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/** FLASH_ECCR_ECCD ECC detection **/
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#define FLASH_ECCR_ECCD (1 << 31)
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/** FLASH_ECCR_ECCC ECC correction **/
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#define FLASH_ECCR_ECCC (1 << 30)
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/** FLASH_ECCR_ECCIE ECC correction interrupt enable **/
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#define FLASH_ECCR_ECCIE (1 << 24)
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/** FLASH_ECCR_SYSF_ECC ECC fail for Corrected ECC Error or Double ECC Error in info block **/
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#define FLASH_ECCR_SYSF_ECC (1 << 20)
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#define FLASH_ECCR_ADDR_ECC_SHIFT 0
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#define FLASH_ECCR_ADDR_ECC_MASK 0x3fff
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/**@}*/
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/** @defgroup flash_optr OPTR Flash option register
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@{*/
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/** FLASH_OPTR_IRHEN Internal reset holder enable bit **/
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#define FLASH_OPTR_IRHEN (1 << 29)
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#define FLASH_OPTR_NRST_MODE_SHIFT 27
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#define FLASH_OPTR_NRST_MODE_MASK 0x03
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/** @defgroup flash_optr_nrst_mode NRST MODE
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* @brief NRST_MODE
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@{*/
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#define FLASH_OPTR_NRST_MODE_RESET 1
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#define FLASH_OPTR_NRST_MODE_GPIO 2
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#define FLASH_OPTR_NRST_MODE_BIDIR 3
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/**@}*/
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/** FLASH_OPTR_nBOOT0 nBOOT0 option bit **/
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#define FLASH_OPTR_nBOOT0 (1 << 26)
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/** FLASH_OPTR_nBOOT1 Boot configuration **/
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#define FLASH_OPTR_nBOOT1 (1 << 25)
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/** FLASH_OPTR_nBOOT_SEL nBOOT_SEL **/
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#define FLASH_OPTR_nBOOT_SEL (1 << 24)
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/** FLASH_OPTR_RAM_PARITY_CHECK SRAM parity check control **/
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#define FLASH_OPTR_RAM_PARITY_CHECK (1 << 22)
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/** FLASH_OPTR_WWDG_SW Window watchdog selection **/
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#define FLASH_OPTR_WWDG_SW (1 << 19)
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/** FLASH_OPTR_IWDG_STDBY Independent watchdog counter freeze in Standby mode **/
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#define FLASH_OPTR_IWDG_STDBY (1 << 18)
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/** FLASH_OPTR_IWDG_STOP Independent watchdog counter freeze in Stop mode **/
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#define FLASH_OPTR_IWDG_STOP (1 << 17)
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/** FLASH_OPTR_IDWG_SW Independent watchdog selection **/
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#define FLASH_OPTR_IDWG_SW (1 << 16)
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/** FLASH_OPTR_nRSTS_HDW nRSTS_HDW **/
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#define FLASH_OPTR_nRSTS_HDW (1 << 15)
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/** FLASH_OPTR_nRST_STDBY nRST_STDBY **/
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#define FLASH_OPTR_nRST_STDBY (1 << 14)
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/** FLASH_OPTR_nRST_STOP nRST_STOP **/
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#define FLASH_OPTR_nRST_STOP (1 << 13)
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#define FLASH_OPTR_BORR_LEV_SHIFT 11
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#define FLASH_OPTR_BORR_LEV_MASK 0x03
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/** @defgroup flash_optr_borr_lev BORR LEV
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* @brief These bits contain the VDD supply level threshold that releases the reset.
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@{*/
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#define FLASH_OPTR_BORR_LEV_2V1 0
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#define FLASH_OPTR_BORR_LEV_2V3 1
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#define FLASH_OPTR_BORR_LEV_2V6 2
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#define FLASH_OPTR_BORR_LEV_2V9 3
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/**@}*/
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#define FLASH_OPTR_BORF_LEV_SHIFT 9
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#define FLASH_OPTR_BORF_LEV_MASK 0x03
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/** @defgroup flash_optr_borf_lev BOR FLEV
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* @brief These bits contain the VDD supply level threshold that activates the reset
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@{*/
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#define FLASH_OPTR_BORF_LEV_2V0 0
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#define FLASH_OPTR_BORF_LEV_2V2 1
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#define FLASH_OPTR_BORF_LEV_2V5 2
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#define FLASH_OPTR_BORF_LEV_2V8 3
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/**@}*/
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/** FLASH_OPTR_BOREN BOR reset Level **/
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#define FLASH_OPTR_BOREN (1 << 8)
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#define FLASH_OPTR_RDP_SHIFT 0
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#define FLASH_OPTR_RDP_MASK 0xff
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/** @defgroup flash_optr_rdp RDP
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* @brief Read protection level
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@{*/
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#define FLASH_OPTR_RDP_LEVEL_0 0xAA
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#define FLASH_OPTR_RDP_LEVEL_1 0xBB /* or any other value. */
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#define FLASH_OPTR_RDP_LEVEL_2 0xCC
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/**@}*/
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/**@}*/
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BEGIN_DECLS
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/** Enable instruction cache */
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void flash_icache_enable(void);
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/** Disable instruction cache */
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void flash_icache_disable(void);
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/** Reset instruction cache */
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void flash_icache_reset(void);
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/** Unlock program memory */
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void flash_unlock_progmem(void);
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/** lock program memory */
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void flash_lock_progmem(void);
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/** Lock Option Byte Access */
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void flash_lock_option_bytes(void);
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END_DECLS
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#endif
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/**@}*/
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