7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
/** @defgroup creg_defines Configuration Registers Defines
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@brief <b>Defined Constants and Types for the LPC43xx Configuration
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Registers</b>
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@ingroup LPC43xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
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@date 10 March 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_CREG_H
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#define LPC43XX_CREG_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- CREG registers ----------------------------------------------------- */
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/*
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* Chip configuration register 32 kHz oscillator output and BOD control
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* register
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*/
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#define CREG_CREG0 MMIO32(CREG_BASE + 0x004)
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/* ARM Cortex-M4 memory mapping */
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#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100)
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/* Chip configuration register 1 */
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#define CREG_CREG1 MMIO32(CREG_BASE + 0x108)
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/* Chip configuration register 2 */
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#define CREG_CREG2 MMIO32(CREG_BASE + 0x10C)
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/* Chip configuration register 3 */
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#define CREG_CREG3 MMIO32(CREG_BASE + 0x110)
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/* Chip configuration register 4 */
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#define CREG_CREG4 MMIO32(CREG_BASE + 0x114)
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/* Chip configuration register 5 */
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#define CREG_CREG5 MMIO32(CREG_BASE + 0x118)
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/* DMA muxing control */
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#define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C)
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/* ETB RAM configuration */
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#define CREG_ETBCFG MMIO32(CREG_BASE + 0x128)
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/*
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* Chip configuration register 6. Controls multiple functions: Ethernet
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* interface, SCT output, I2S0/1 inputs, EMC clock.
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*/
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#define CREG_CREG6 MMIO32(CREG_BASE + 0x12C)
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/* Cortex-M4 TXEV event clear */
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#define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130)
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/* Part ID */
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#define CREG_CHIPID MMIO32(CREG_BASE + 0x200)
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/* Cortex-M0 TXEV event clear */
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#define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400)
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/* ARM Cortex-M0 memory mapping */
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#define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404)
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/**@}*/
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#endif
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