7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
158 lines
5.0 KiB
C
158 lines
5.0 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_USB_H
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#define LPC43XX_USB_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- USB0 registers ------------------------------------------------------ */
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/* Device/host capability registers */
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/* Capability register length */
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#define USB0_CAPLENGTH MMIO32(USB0_BASE + 0x100)
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/* Host controller structural parameters */
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#define USB0_HCSPARAMS MMIO32(USB0_BASE + 0x104)
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/* Host controller capability parameters */
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#define USB0_HCCPARAMS MMIO32(USB0_BASE + 0x108)
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/* Device interface version number */
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#define USB0_DCIVERSION MMIO32(USB0_BASE + 0x120)
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/* Device controller capability parameters */
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#define USB0_DCCPARAMS MMIO32(USB0_BASE + 0x124)
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/* Device/host operational registers */
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/* USB command (device mode) */
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#define USB0_USBCMD_D MMIO32(USB0_BASE + 0x140)
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/* USB command (host mode) */
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#define USB0_USBCMD_H MMIO32(USB0_BASE + 0x140)
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/* USB status (device mode) */
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#define USB0_USBSTS_D MMIO32(USB0_BASE + 0x144)
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/* USB status (host mode) */
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#define USB0_USBSTS_H MMIO32(USB0_BASE + 0x144)
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/* USB interrupt enable (device mode) */
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#define USB0_USBINTR_D MMIO32(USB0_BASE + 0x148)
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/* USB interrupt enable (host mode) */
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#define USB0_USBINTR_H MMIO32(USB0_BASE + 0x148)
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/* USB frame index (device mode) */
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#define USB0_FRINDEX_D MMIO32(USB0_BASE + 0x14C)
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/* USB frame index (host mode) */
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#define USB0_FRINDEX_H MMIO32(USB0_BASE + 0x14C)
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/* USB device address (device mode) */
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#define USB0_DEVICEADDR MMIO32(USB0_BASE + 0x154)
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/* Frame list base address (host mode) */
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#define USB0_PERIODICLISTBASE MMIO32(USB0_BASE + 0x154)
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/* Address of endpoint list in memory */
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#define USB0_ENDPOINTLISTADDR MMIO32(USB0_BASE + 0x158)
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/* Asynchronous list address */
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#define USB0_ASYNCLISTADDR MMIO32(USB0_BASE + 0x158)
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/* Asynchronous buffer status for embedded TT (host mode) */
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#define USB0_TTCTRL MMIO32(USB0_BASE + 0x15C)
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/* Programmable burst size */
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#define USB0_BURSTSIZE MMIO32(USB0_BASE + 0x160)
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/* Host transmit pre-buffer packet tuning (host mode) */
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#define USB0_TXFILLTUNING MMIO32(USB0_BASE + 0x164)
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/* Length of virtual frame */
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#define USB0_BINTERVAL MMIO32(USB0_BASE + 0x174)
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/* Endpoint NAK (device mode) */
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#define USB0_ENDPTNAK MMIO32(USB0_BASE + 0x178)
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/* Endpoint NAK Enable (device mode) */
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#define USB0_ENDPTNAKEN MMIO32(USB0_BASE + 0x17C)
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/* Port 1 status/control (device mode) */
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#define USB0_PORTSC1_D MMIO32(USB0_BASE + 0x184)
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/* Port 1 status/control (host mode) */
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#define USB0_PORTSC1_H MMIO32(USB0_BASE + 0x184)
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/* OTG status and control */
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#define USB0_OTGSC MMIO32(USB0_BASE + 0x1A4)
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/* USB device mode (device mode) */
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#define USB0_USBMODE_D MMIO32(USB0_BASE + 0x1A8)
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/* USB device mode (host mode) */
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#define USB0_USBMODE_H MMIO32(USB0_BASE + 0x1A8)
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/* Device endpoint registers */
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/* Endpoint setup status */
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#define USB0_ENDPTSETUPSTAT MMIO32(USB0_BASE + 0x1AC)
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/* Endpoint initialization */
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#define USB0_ENDPTPRIME MMIO32(USB0_BASE + 0x1B0)
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/* Endpoint de-initialization */
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#define USB0_ENDPTFLUSH MMIO32(USB0_BASE + 0x1B4)
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/* Endpoint status */
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#define USB0_ENDPTSTAT MMIO32(USB0_BASE + 0x1B8)
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/* Endpoint complete */
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#define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC)
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/* Endpoint control 0 */
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#define USB0_ENDPTCTRL0 MMIO32(USB0_BASE + 0x1C0)
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/* Endpoint control 1 */
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#define USB0_ENDPTCTRL1 MMIO32(USB0_BASE + 0x1C4)
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/* Endpoint control 2 */
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#define USB0_ENDPTCTRL2 MMIO32(USB0_BASE + 0x1C8)
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/* Endpoint control 3 */
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#define USB0_ENDPTCTRL3 MMIO32(USB0_BASE + 0x1CC)
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/* Endpoint control 4 */
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#define USB0_ENDPTCTRL4 MMIO32(USB0_BASE + 0x1D0)
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/* Endpoint control 5 */
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#define USB0_ENDPTCTRL5 MMIO32(USB0_BASE + 0x1D4)
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/* --- USB1 registers ------------------------------------------------------ */
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/* TODO */
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#endif
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