7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
84 lines
2.8 KiB
C
84 lines
2.8 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SAM3X_EEFC_H
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#define SAM3X_EEFC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/sam/memorymap.h>
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/* --- Convenience macros ------------------------------------------------ */
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#define EEFC EEFC_BASE
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#define EEFC0 EEFC0_BASE
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#define EEFC1 EEFC1_BASE
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/* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */
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#define EEFC_FMR(port) MMIO32((port) + 0x00)
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#define EEFC_FCR(port) MMIO32((port) + 0x04)
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#define EEFC_FSR(port) MMIO32((port) + 0x08)
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#define EEFC_FRR(port) MMIO32((port) + 0x0C)
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/* 0x0010 - Reserved */
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/* EEFC Flash Mode Register (EEFC_FMR) */
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/* Bit [31:25] - Reserved */
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#define EEFC_FMR_FAM (0x01 << 24)
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/* Bit [23:12] - Reserved */
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#define EEFC_FMR_FWS_MASK (0x0F << 8)
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/* Bit [7:1] - Reserved */
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#define EEFC_FMR_FRDY (0x01 << 0)
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/* EEFC Flash Command Register (EEFC_FCR) */
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#define EEFC_FCR_FKEY (0x5A << 24)
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#define EEFC_FCR_FARG_MASK (0xFFFF << 8)
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#define EEFC_FCR_FCMD_MASK (0xFF << 0)
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#define EEFC_FCR_FCMD_GETD (0x00 << 0)
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#define EEFC_FCR_FCMD_WP (0x01 << 0)
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#define EEFC_FCR_FCMD_WPL (0x02 << 0)
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#define EEFC_FCR_FCMD_EWP (0x03 << 0)
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#define EEFC_FCR_FCMD_EWPL (0x04 << 0)
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#define EEFC_FCR_FCMD_EA (0x05 << 0)
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#define EEFC_FCR_FCMD_SLB (0x08 << 0)
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#define EEFC_FCR_FCMD_CLB (0x09 << 0)
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#define EEFC_FCR_FCMD_GLB (0x0A << 0)
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#define EEFC_FCR_FCMD_SGPB (0x0B << 0)
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#define EEFC_FCR_FCMD_CGPB (0x0C << 0)
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#define EEFC_FCR_FCMD_GGPB (0x0D << 0)
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#define EEFC_FCR_FCMD_STUI (0x0E << 0)
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#define EEFC_FCR_FCMD_SPUI (0x0F << 0)
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/* EEFC Flash Status Register (EEFC_FSR) */
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/* Bit [31:3] - Reserved */
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#define EEFC_FSR_FLOCKE (0x01 << 2)
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#define EEFC_FSR_FCMDE (0x01 << 1)
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#define EEFC_FSR_FRDY (0x01 << 0)
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static inline void eefc_set_latency(u8 wait)
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{
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#if defined(SAM3X)
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EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
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EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
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#elif defined(SAM3N)
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EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
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#endif
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}
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#endif
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