7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
422 lines
14 KiB
C
422 lines
14 KiB
C
/** @addtogroup dac_defines
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@author @htmlonly © @endhtmlonly 2012
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Felix Held <felix-libopencm3@felixheld.de>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H
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The order of header inclusion is important. dac.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_DAC_H
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/** @endcond */
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#ifndef LIBOPENCM3_DAC_COMMON_ALL_H
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#define LIBOPENCM3_DAC_COMMON_ALL_H
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#include <libopencm3/cm3/common.h>
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/* --- DAC registers ------------------------------------------------------- */
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/* DAC control register (DAC_CR) */
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#define DAC_CR MMIO32(DAC_BASE + 0x00)
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/* DAC software trigger register (DAC_SWTRIGR) */
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#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
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/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
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#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
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/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
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#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
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/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
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#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
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/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
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#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14)
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/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
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#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18)
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/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
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#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C)
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/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
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#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20)
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/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
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#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24)
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/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
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#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28)
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/* DAC channel1 data output register (DAC_DOR1) */
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#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
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/* DAC channel2 data output register (DAC_DOR2) */
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#define DAC_DOR2 MMIO32(DAC_BASE + 0x30)
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/* --- DAC_CR values ------------------------------------------------------- */
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/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
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/* doesn't exist in most members of the STM32F1 family */
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#define DAC_CR_DMAUDRIE2 (1 << 29)
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/* DMAEN2: DAC channel2 DMA enable */
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#define DAC_CR_DMAEN2 (1 << 28)
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/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
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/* DAC_CR_MAMP2_n:
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* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
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*/
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#define DAC_CR_MAMP2_SHIFT 24
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/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
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@ingroup dac_defines
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Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
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@{*/
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#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
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/**@}*/
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/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
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/* Legend:
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* DIS: wave generation disabled
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* NOISE: Noise wave generation enabled
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* TRI: Triangle wave generation enabled
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*
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* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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*/
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#define DAC_CR_WAVE2_SHIFT 22
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#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
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/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
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@ingroup dac_defines
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@li NOISE: Noise wave generation enabled
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@li TRI: Triangle wave generation enabled
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@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
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@{*/
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#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
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#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
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/**@}*/
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/* TSEL2[2:0]: DAC channel2 trigger selection */
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/* Legend:
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*
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* T6: Timer 6 TRGO event
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* T3: Timer 3 TRGO event
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* T8: Timer 8 TRGO event
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* T7: Timer 7 TRGO event
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* T5: Timer 5 TRGO event
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* T15: Timer 15 TRGO event
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* T2: Timer 2 TRGO event
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* T4: Timer 4 TRGO event
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* E9: External line9
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* SW: Software trigger
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*
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* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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* Note: T3 == T8; T5 == T15; not both present on one device
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* Note: this is *not* valid for the STM32L1 family
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*/
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#define DAC_CR_TSEL2_SHIFT 19
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/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
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@ingroup dac_defines
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@li T6: Timer 6 TRGO event
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@li T3: Timer 3 TRGO event
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@li T8: Timer 8 TRGO event
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@li T7: Timer 7 TRGO event
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@li T5: Timer 5 TRGO event
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@li T15: Timer 15 TRGO event
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@li T2: Timer 2 TRGO event
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@li T4: Timer 4 TRGO event
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@li E9: External line9
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@li SW: Software trigger
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@note: Refer to the timer documentation for details of the TRGO event.
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@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
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@note: this is <b>not</b> valid for the STM32L1 family.
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@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
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@{*/
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#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
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/**@}*/
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/* TEN2: DAC channel2 trigger enable */
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#define DAC_CR_TEN2 (1 << 18)
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/* BOFF2: DAC channel2 output buffer disable */
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#define DAC_CR_BOFF2 (1 << 17)
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/* EN2: DAC channel2 enable */
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#define DAC_CR_EN2 (1 << 16)
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/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
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/* doesn't exist in most members of the STM32F1 family */
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#define DAC_CR_DMAUDRIE1 (1 << 13)
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/* DMAEN1: DAC channel1 DMA enable */
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#define DAC_CR_DMAEN1 (1 << 12)
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/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
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/* DAC_CR_MAMP1_n:
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* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
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*/
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#define DAC_CR_MAMP1_SHIFT 8
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/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
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@ingroup dac_defines
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Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
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@{*/
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#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
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/**@}*/
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/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
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/* Legend:
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* DIS: wave generation disabled
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* NOISE: Noise wave generation enabled
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* TRI: Triangle wave generation enabled
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*
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* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
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*/
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#define DAC_CR_WAVE1_SHIFT 6
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#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
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/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
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@ingroup dac_defines
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@li DIS: wave generation disabled
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@li NOISE: Noise wave generation enabled
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@li TRI: Triangle wave generation enabled
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@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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@{*/
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#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
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#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
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/**@}*/
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/* TSEL1[2:0]: DAC channel1 trigger selection */
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/* Legend:
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*
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* T6: Timer 6 TRGO event
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* T3: Timer 3 TRGO event in connectivity line devices
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* T8: Timer 8 TRGO event in high-density and XL-density devices
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* T7: Timer 7 TRGO event
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* T5: Timer 5 TRGO event
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* T15: Timer 15 TRGO event
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* T2: Timer 2 TRGO event
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* T4: Timer 4 TRGO event
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* E9: External line9
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* SW: Software trigger
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*
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* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
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* Note: T3 == T8; T5 == T15; not both present on one device
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* Note: this is *not* valid for the STM32L1 family
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*/
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#define DAC_CR_TSEL1_SHIFT 3
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/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
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@ingroup dac_defines
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@li T6: Timer 6 TRGO event
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@li T3: Timer 3 TRGO event
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@li T8: Timer 8 TRGO event
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@li T7: Timer 7 TRGO event
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@li T5: Timer 5 TRGO event
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@li T15: Timer 15 TRGO event
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@li T2: Timer 2 TRGO event
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@li T4: Timer 4 TRGO event
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@li E9: External line 9
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@li SW: Software trigger
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@note: Refer to the timer documentation for details of the TRGO event.
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@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
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@note: this is <b>not</b> valid for the STM32L1 family.
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@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
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@{*/
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#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
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/**@}*/
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/* TEN1: DAC channel1 trigger enable */
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#define DAC_CR_TEN1 (1 << 2)
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/* BOFF1: DAC channel1 output buffer disable */
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#define DAC_CR_BOFF1 (1 << 1)
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/* EN1: DAC channel1 enable */
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#define DAC_CR_EN1 (1 << 0)
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/* --- DAC_SWTRIGR values -------------------------------------------------- */
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/* SWTRIG2: DAC channel2 software trigger */
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#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
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/* SWTRIG1: DAC channel1 software trigger */
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#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
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/* --- DAC_DHR12R1 values -------------------------------------------------- */
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#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0)
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#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0)
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/* --- DAC_DHR12L1 values -------------------------------------------------- */
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#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4)
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#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4)
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/* --- DAC_DHR8R1 values --------------------------------------------------- */
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#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0)
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#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0)
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/* --- DAC_DHR12R2 values -------------------------------------------------- */
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#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0)
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#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0)
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/* --- DAC_DHR12L2 values -------------------------------------------------- */
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#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4)
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#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4)
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/* --- DAC_DHR8R2 values --------------------------------------------------- */
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#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0)
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#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0)
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/* --- DAC_DHR12RD values -------------------------------------------------- */
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#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16)
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#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16)
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#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0)
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#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0)
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/* --- DAC_DHR12LD values -------------------------------------------------- */
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#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16)
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#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20)
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#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0)
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#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4)
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/* --- DAC_DHR8RD values --------------------------------------------------- */
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#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8)
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#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8)
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#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0)
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#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0)
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/* --- DAC_DOR1 values ----------------------------------------------------- */
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#define DAC_DOR1_DACC1DOR_LSB (1 << 0)
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#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0)
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/* --- DAC_DOR2 values ----------------------------------------------------- */
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#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
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#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
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/** DAC channel identifier */
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typedef enum {
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CHANNEL_1, CHANNEL_2, CHANNEL_D
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} data_channel;
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/** DAC data size (8/12 bits), alignment (right/left) */
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typedef enum {
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RIGHT8, RIGHT12, LEFT12
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} data_align;
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void dac_enable(data_channel dac_channel);
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void dac_disable(data_channel dac_channel);
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void dac_buffer_enable(data_channel dac_channel);
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void dac_buffer_disable(data_channel dac_channel);
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void dac_dma_enable(data_channel dac_channel);
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void dac_dma_disable(data_channel dac_channel);
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void dac_trigger_enable(data_channel dac_channel);
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void dac_trigger_disable(data_channel dac_channel);
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void dac_set_trigger_source(u32 dac_trig_src);
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void dac_set_waveform_generation(u32 dac_wave_ens);
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void dac_disable_waveform_generation(data_channel dac_channel);
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void dac_set_waveform_characteristics(u32 dac_mamp);
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void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_channel dac_channel);
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void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2, data_align dac_data_format);
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void dac_software_trigger(data_channel dac_channel);
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END_DECLS
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#endif
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/** @cond */
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#else
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#warning "dac_common_all.h should not be included explicitly, only via dac.h"
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#endif
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/** @endcond */
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/**@}*/
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