7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
280 lines
9.3 KiB
C
280 lines
9.3 KiB
C
/** @defgroup adc_defines USB Defines
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@brief <b>Defined Constants and Types for the STM32F1xx USB Module</b>
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@ingroup STM32F1xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009
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Piotr Esden-Tempski <piotr@esden.net>
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@date 11 March 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_USB_H
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#define LIBOPENCM3_USB_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/tools.h>
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/* --- USB base addresses -------------------------------------------------- */
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/* USB packet buffer memory base addr. */
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#define USB_PMA_BASE 0x40006000L
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/* --- USB general registers ----------------------------------------------- */
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/* USB Control register */
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#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
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/* USB Interrupt status register */
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#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44))
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/* USB Frame number register */
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#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48))
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/* USB Device address register */
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#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C))
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/* USB Buffer table address register */
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#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50))
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/* USB EP register */
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#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
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/* --- USB control register masks / bits ----------------------------------- */
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/* Interrupt mask bits, set to 1 to enable interrupt generation */
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#define USB_CNTR_CTRM 0x8000
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#define USB_CNTR_PMAOVRM 0x4000
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#define USB_CNTR_ERRM 0x2000
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#define USB_CNTR_WKUPM 0x1000
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#define USB_CNTR_SUSPM 0x0800
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#define USB_CNTR_RESETM 0x0400
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#define USB_CNTR_SOFM 0x0200
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#define USB_CNTR_ESOFM 0x0100
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/* Request/Force bits */
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#define USB_CNTR_RESUME 0x0010 /* Resume request */
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#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
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#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
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#define USB_CNTR_PWDN 0x0002 /* Power down */
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#define USB_CNTR_FRES 0x0001 /* Force reset */
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/* --- USB interrupt status register masks / bits -------------------------- */
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#define USB_ISTR_CTR 0x8000 /* Correct Transfer */
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#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
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#define USB_ISTR_ERR 0x2000 /* Error */
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#define USB_ISTR_WKUP 0x1000 /* Wake up */
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#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */
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#define USB_ISTR_RESET 0x0400 /* USB RESET request */
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#define USB_ISTR_SOF 0x0200 /* Start Of Frame */
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#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */
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#define USB_ISTR_DIR 0x0010 /* Direction of transaction */
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#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
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/* --- USB interrupt status register manipulators -------------------------- */
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/* Note: CTR is read only! */
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#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
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#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
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#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
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#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP)
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#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET)
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#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
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#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
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/* --- USB device addres register masks / bits ----------------------------- */
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#define USB_DADDR_ENABLE 0x0080
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#define USB_DADDR_ADDR 0x007F
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/* --- USB device addres register manipulators ----------------------------- */
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/* --- USB endpoint register offsets --------------------------------------- */
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#define USB_EP0 0
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#define USB_EP1 1
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#define USB_EP2 2
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#define USB_EP3 3
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#define USB_EP4 4
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#define USB_EP5 5
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#define USB_EP6 6
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#define USB_EP7 7
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/* --- USB endpoint register masks / bits ---------------------------------- */
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/* Masks and toggle bits */
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#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
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#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
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#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
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#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
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#define USB_EP_TYPE 0x0600 /* Endpoint type */
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#define USB_EP_KIND 0x0100 /* Endpoint kind.
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* When set and type=bulk -> double buffer
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* When set and type=control -> status out
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*/
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#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
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#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
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#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
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#define USB_EP_ADDR 0x000F /* Endpoint Address */
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/* Masking all toggle bits */
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#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
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USB_EP_SETUP | \
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USB_EP_TYPE | \
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USB_EP_KIND | \
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USB_EP_TX_CTR | \
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USB_EP_ADDR)
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/* All non toggle bits plus EP_RX toggle bits */
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#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK)
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/* All non toggle bits plus EP_TX toggle bits */
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#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
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/* Endpoint status bits for USB_EP_RX_STAT bit field */
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#define USB_EP_RX_STAT_DISABLED 0x0000
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#define USB_EP_RX_STAT_STALL 0x1000
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#define USB_EP_RX_STAT_NAK 0x2000
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#define USB_EP_RX_STAT_VALID 0x3000
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/* Endpoint status bits for USB_EP_TX_STAT bit field */
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#define USB_EP_TX_STAT_DISABLED 0x0000
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#define USB_EP_TX_STAT_STALL 0x0010
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#define USB_EP_TX_STAT_NAK 0x0020
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#define USB_EP_TX_STAT_VALID 0x0030
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/* Endpoint type bits for USB_EP_TYPE bit field */
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#define USB_EP_TYPE_BULK 0x0000
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#define USB_EP_TYPE_CONTROL 0x0200
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#define USB_EP_TYPE_ISO 0x0400
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#define USB_EP_TYPE_INTERRUPT 0x0600
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/* --- USB endpoint register manipulators ---------------------------------- */
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/*
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* Set USB endpoint tx/rx status.
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*
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* USB status field is changed using an awkward toggle mechanism, that
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* is why we use some helper macros for that.
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*/
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#define USB_SET_EP_RX_STAT(EP, STAT) \
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TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT)
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#define USB_SET_EP_TX_STAT(EP, STAT) \
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TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT)
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/*
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* Macros for clearing and setting USB endpoint register bits that do
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* not use the toggle mechanism.
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*
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* Because the register contains some bits that use the toggle
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* mechanism we need a helper macro here. Otherwise the code gets really messy.
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*/
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#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \
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CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT)
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#define USB_CLR_EP_RX_CTR(EP) \
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USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR)
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#define USB_CLR_EP_TX_CTR(EP) \
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USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR)
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#define USB_SET_EP_TYPE(EP, TYPE) \
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SET_REG(USB_EP_REG(EP), \
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(GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & \
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(~USB_EP_TYPE))) | TYPE)
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#define USB_SET_EP_KIND(EP) \
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SET_REG(USB_EP_REG(EP), \
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(GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & \
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(~USB_EP_KIND))) | USB_EP_KIND)
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#define USB_CLR_EP_KIND(EP) \
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SET_REG(USB_EP_REG(EP), \
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(GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
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#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
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#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
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#define USB_SET_EP_ADDR(EP, ADDR) \
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SET_REG(USB_EP_REG(EP), \
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((GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & \
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(~USB_EP_ADDR))) | ADDR))
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/* Macros for clearing DTOG bits */
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#define USB_CLR_EP_TX_DTOG(EP) \
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SET_REG(USB_EP_REG(EP), \
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GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG))
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#define USB_CLR_EP_RX_DTOG(EP) \
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SET_REG(USB_EP_REG(EP), \
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GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))
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/* --- USB BTABLE registers ------------------------------------------------ */
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#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
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#define USB_EP_TX_ADDR(EP) \
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((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
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#define USB_EP_TX_COUNT(EP) \
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((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
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#define USB_EP_RX_ADDR(EP) \
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((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
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#define USB_EP_RX_COUNT(EP) \
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((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
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/* --- USB BTABLE manipulators --------------------------------------------- */
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#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
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#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
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#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
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#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
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#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
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#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
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#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
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#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
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#define USB_GET_EP_TX_BUFF(EP) \
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(USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))
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#define USB_GET_EP_RX_BUFF(EP) \
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(USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2))
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#endif
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/**@}*/
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