7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/** @defgroup timer_defines Timer Defines
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@brief <b>libopencm3 Defined Constants and Types for the STM32L1xx Timers</b>
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@ingroup STM32L1xx_defines
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@version 1.0.0
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@date 8 March 2013
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_TIMER_H
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#define LIBOPENCM3_TIMER_H
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#include <libopencm3/stm32/common/timer_common_all.h>
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/*
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* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
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* CNT, ARR, CCR1, CCR2, CCR3, CCR4
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*/
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/* Timer 2/3 option register (TIMx_OR) */
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#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
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#define TIM2_OR TIM_OR(TIM2)
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#define TIM3_OR TIM_OR(TIM3)
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/* --- TIMx_OR values ---------------------------------------------------- */
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/* ITR1_RMP */
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/****************************************************************************/
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/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal
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Trigger 1 Remap
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@ingroup timer_defines
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@{*/
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/** Internal Trigger 1 remapped to timer 10 output compare */
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#define TIM2_OR_ITR1_RMP_TIM10_OC (0x0 << 0)
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/** Internal Trigger 1 remapped to timer 5 TGO */
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#define TIM2_OR_ITR1_RMP_TIM5_TGO (0x1 << 0)
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/**@}*/
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#define TIM3_OR_ITR1_RMP_MASK (0x1 << 0)
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/* --- TIMx_OR values ---------------------------------------------------- */
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/* ITR2_RMP */
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/****************************************************************************/
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/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Option Register Internal Trigger 2 Remap
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@ingroup timer_defines
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@{*/
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/** Internal Trigger 1 remapped to timer 11 output compare */
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#define TIM3_OR_ITR2_RMP_TIM8_TRGOU (0x0 << 0)
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/** Internal Trigger 1 remapped to timer 5 TGO */
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#define TIM3_OR_ITR2_RMP_PTP (0x1 << 0)
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/**@}*/
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#define TIM3_OR_ITR2_RMP_MASK (0x1 << 0)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void timer_set_option(u32 timer_peripheral, u32 option);
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END_DECLS
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#endif
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