7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
400 lines
15 KiB
C
400 lines
15 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_OTG_HS_H
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#define LIBOPENCM3_OTG_HS_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* Core Global Control and Status Registers */
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#define OTG_GOTGCTL 0x000
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#define OTG_GOTGIN 0x004
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#define OTG_GAHBCFG 0x008
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#define OTG_GUSBCFG 0x00C
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#define OTG_GRSTCTL 0x010
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#define OTG_GINTSTS 0x014
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#define OTG_GINTMSK 0x018
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#define OTG_GRXSTSR 0x01C
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#define OTG_GRXSTSP 0x020
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#define OTG_GRXFSIZ 0x024
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#define OTG_GNPTXFSIZ 0x028
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#define OTG_GNPTXSTS 0x02C
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#define OTG_GCCFG 0x038
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#define OTG_CID 0x03C
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#define OTG_HPTXFSIZ 0x100
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#define OTG_DIEPTXF(x) (0x104 + 4*(x-1))
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/* Host-mode Control and Status Registers */
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#define OTG_HCFG 0x400
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#define OTG_HFIR 0x404
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#define OTG_HFNUM 0x408
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#define OTG_HPTXSTS 0x410
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#define OTG_HAINT 0x414
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#define OTG_HAINTMSK 0x418
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#define OTG_HPRT 0x440
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#define OTG_HCCHARx 0x500
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#define OTG_HCINTx 0x508
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#define OTG_HCINTMSKx 0x50C
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#define OTG_HCTSIZx 0x510
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/* Device-mode Control and Status Registers */
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#define OTG_DCFG 0x800
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#define OTG_DCTL 0x804
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#define OTG_DSTS 0x808
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#define OTG_DIEPMSK 0x810
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#define OTG_DOEPMSK 0x814
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#define OTG_DAINT 0x818
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#define OTG_DAINTMSK 0x81C
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#define OTG_DVBUSDIS 0x828
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#define OTG_DVBUSPULSE 0x82C
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#define OTG_DIEPEMPMSK 0x834
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#define OTG_DIEPCTL0 0x900
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#define OTG_DIEPCTL(x) (0x900 + 0x20*(x))
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#define OTG_DOEPCTL0 0xB00
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#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x))
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#define OTG_DIEPINT(x) (0x908 + 0x20*(x))
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#define OTG_DOEPINT(x) (0xB08 + 0x20*(x))
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#define OTG_DIEPTSIZ0 0x910
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#define OTG_DOEPTSIZ0 0xB10
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#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x))
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#define OTG_DTXFSTS(x) (0x918 + 0x20*(x))
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#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x))
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/* Power and clock gating control and status register */
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#define OTG_PCGCCTL 0xE00
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/* Data FIFO */
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#define OTG_FIFO(x) (((x) + 1) << 12)
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/***********************************************************************/
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/* Core Global Control and Status Registers */
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#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
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#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
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#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
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#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
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#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
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#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
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#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
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#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
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#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
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#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
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#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
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#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
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#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
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#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID)
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#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
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#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
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/* Host-mode Control and Status Registers */
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#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
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#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
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#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
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#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
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#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
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#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
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#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
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#define OTG_HS_HCCHARx MMIO32(USB_OTG_HS_BASE + OTG_HCCHARx)
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#define OTG_HS_HCINTx MMIO32(USB_OTG_HS_BASE + OTG_HCINTx)
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#define OTG_HS_HCINTMSKx MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSKx)
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#define OTG_HS_HCTSIZx MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZx)
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/* Device-mode Control and Status Registers */
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#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
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#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
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#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
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#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
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#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
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#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
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#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
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#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
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#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
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#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
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#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
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#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
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#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
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#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
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#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
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#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
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#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
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#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
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#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
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OTG_DIEPTSIZ(x))
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#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
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#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
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OTG_DOEPTSIZ(x))
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/* Power and clock gating control and status register */
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#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
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/* Data FIFO */
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#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + \
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OTG_FIFO(x)))
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/* Global CSRs */
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/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */
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#define OTG_HS_GOTGCTL_BSVLD (1 << 19)
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#define OTG_HS_GOTGCTL_ASVLD (1 << 18)
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#define OTG_HS_GOTGCTL_DBCT (1 << 17)
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#define OTG_HS_GOTGCTL_CIDSTS (1 << 16)
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#define OTG_HS_GOTGCTL_DHNPEN (1 << 11)
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#define OTG_HS_GOTGCTL_HSHNPEN (1 << 10)
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#define OTG_HS_GOTGCTL_HNPRQ (1 << 9)
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#define OTG_HS_GOTGCTL_HNGSCS (1 << 8)
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#define OTG_HS_GOTGCTL_SRQ (1 << 1)
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#define OTG_HS_GOTGCTL_SRQSCS (1 << 0)
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/* OTG_FS AHB configuration register (OTG_HS_GAHBCFG) */
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#define OTG_HS_GAHBCFG_GINT 0x0001
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#define OTG_HS_GAHBCFG_TXFELVL 0x0080
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#define OTG_HS_GAHBCFG_PTXFELVL 0x0100
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/* OTG_FS USB configuration register (OTG_HS_GUSBCFG) */
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#define OTG_HS_GUSBCFG_TOCAL 0x00000003
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#define OTG_HS_GUSBCFG_SRPCAP 0x00000100
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#define OTG_HS_GUSBCFG_HNPCAP 0x00000200
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#define OTG_HS_GUSBCFG_TRDT_MASK (0xf << 10)
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#define OTG_HS_GUSBCFG_TRDT_16BIT (0x5 << 10)
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#define OTG_HS_GUSBCFG_TRDT_8BIT (0x9 << 10)
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#define OTG_HS_GUSBCFG_NPTXRWEN 0x00004000
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#define OTG_HS_GUSBCFG_FHMOD 0x20000000
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#define OTG_HS_GUSBCFG_FDMOD 0x40000000
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#define OTG_HS_GUSBCFG_CTXPKT 0x80000000
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#define OTG_HS_GUSBCFG_PHYSEL (1 << 6)
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/* OTG_FS reset register (OTG_HS_GRSTCTL) */
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#define OTG_HS_GRSTCTL_AHBIDL (1 << 31)
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/* Bits 30:11 - Reserved */
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#define OTG_HS_GRSTCTL_TXFNUM_MASK (0x1f << 6)
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#define OTG_HS_GRSTCTL_TXFFLSH (1 << 5)
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#define OTG_HS_GRSTCTL_RXFFLSH (1 << 4)
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/* Bit 3 - Reserved */
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#define OTG_HS_GRSTCTL_FCRST (1 << 2)
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#define OTG_HS_GRSTCTL_HSRST (1 << 1)
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#define OTG_HS_GRSTCTL_CSRST (1 << 0)
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/* OTG_FS interrupt status register (OTG_HS_GINTSTS) */
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#define OTG_HS_GINTSTS_WKUPINT (1 << 31)
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#define OTG_HS_GINTSTS_SRQINT (1 << 30)
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#define OTG_HS_GINTSTS_DISCINT (1 << 29)
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#define OTG_HS_GINTSTS_CIDSCHG (1 << 28)
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/* Bit 27 - Reserved */
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#define OTG_HS_GINTSTS_PTXFE (1 << 26)
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#define OTG_HS_GINTSTS_HCINT (1 << 25)
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#define OTG_HS_GINTSTS_HPRTINT (1 << 24)
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/* Bits 23:22 - Reserved */
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#define OTG_HS_GINTSTS_IPXFR (1 << 21)
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#define OTG_HS_GINTSTS_INCOMPISOOUT (1 << 21)
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#define OTG_HS_GINTSTS_IISOIXFR (1 << 20)
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#define OTG_HS_GINTSTS_OEPINT (1 << 19)
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#define OTG_HS_GINTSTS_IEPINT (1 << 18)
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/* Bits 17:16 - Reserved */
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#define OTG_HS_GINTSTS_EOPF (1 << 15)
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#define OTG_HS_GINTSTS_ISOODRP (1 << 14)
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#define OTG_HS_GINTSTS_ENUMDNE (1 << 13)
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#define OTG_HS_GINTSTS_USBRST (1 << 12)
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#define OTG_HS_GINTSTS_USBSUSP (1 << 11)
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#define OTG_HS_GINTSTS_ESUSP (1 << 10)
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/* Bits 9:8 - Reserved */
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#define OTG_HS_GINTSTS_GONAKEFF (1 << 7)
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#define OTG_HS_GINTSTS_GINAKEFF (1 << 6)
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#define OTG_HS_GINTSTS_NPTXFE (1 << 5)
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#define OTG_HS_GINTSTS_RXFLVL (1 << 4)
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#define OTG_HS_GINTSTS_SOF (1 << 3)
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#define OTG_HS_GINTSTS_OTGINT (1 << 2)
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#define OTG_HS_GINTSTS_MMIS (1 << 1)
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#define OTG_HS_GINTSTS_CMOD (1 << 0)
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/* OTG_FS interrupt mask register (OTG_HS_GINTMSK) */
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#define OTG_HS_GINTMSK_MMISM 0x00000002
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#define OTG_HS_GINTMSK_OTGINT 0x00000004
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#define OTG_HS_GINTMSK_SOFM 0x00000008
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#define OTG_HS_GINTMSK_RXFLVLM 0x00000010
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#define OTG_HS_GINTMSK_NPTXFEM 0x00000020
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#define OTG_HS_GINTMSK_GINAKEFFM 0x00000040
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#define OTG_HS_GINTMSK_GONAKEFFM 0x00000080
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#define OTG_HS_GINTMSK_ESUSPM 0x00000400
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#define OTG_HS_GINTMSK_USBSUSPM 0x00000800
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#define OTG_HS_GINTMSK_USBRST 0x00001000
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#define OTG_HS_GINTMSK_ENUMDNEM 0x00002000
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#define OTG_HS_GINTMSK_ISOODRPM 0x00004000
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#define OTG_HS_GINTMSK_EOPFM 0x00008000
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#define OTG_HS_GINTMSK_EPMISM 0x00020000
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#define OTG_HS_GINTMSK_IEPINT 0x00040000
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#define OTG_HS_GINTMSK_OEPINT 0x00080000
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#define OTG_HS_GINTMSK_IISOIXFRM 0x00100000
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#define OTG_HS_GINTMSK_IISOOXFRM 0x00200000
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#define OTG_HS_GINTMSK_IPXFRM 0x00200000
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#define OTG_HS_GINTMSK_PRTIM 0x01000000
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#define OTG_HS_GINTMSK_HCIM 0x02000000
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#define OTG_HS_GINTMSK_PTXFEM 0x04000000
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#define OTG_HS_GINTMSK_CIDSCHGM 0x10000000
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#define OTG_HS_GINTMSK_DISCINT 0x20000000
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#define OTG_HS_GINTMSK_SRQIM 0x40000000
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#define OTG_HS_GINTMSK_WUIM 0x80000000
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/* OTG_FS Receive Status Pop Register (OTG_HS_GRXSTSP) */
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/* Bits 31:25 - Reserved */
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#define OTG_HS_GRXSTSP_FRMNUM_MASK (0xf << 21)
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#define OTG_HS_GRXSTSP_PKTSTS_MASK (0xf << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_OUT (0x2 << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
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#define OTG_HS_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
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#define OTG_HS_GRXSTSP_DPID_MASK (0x3 << 15)
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#define OTG_HS_GRXSTSP_DPID_DATA0 (0x0 << 15)
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#define OTG_HS_GRXSTSP_DPID_DATA1 (0x2 << 15)
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#define OTG_HS_GRXSTSP_DPID_DATA2 (0x1 << 15)
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#define OTG_HS_GRXSTSP_DPID_MDATA (0x3 << 15)
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#define OTG_HS_GRXSTSP_BCNT_MASK (0x7ff << 4)
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#define OTG_HS_GRXSTSP_EPNUM_MASK (0xf << 0)
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/* OTG_FS general core configuration register (OTG_HS_GCCFG) */
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/* Bits 31:21 - Reserved */
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#define OTG_HS_GCCFG_SOFOUTEN (1 << 20)
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#define OTG_HS_GCCFG_VBUSBSEN (1 << 19)
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#define OTG_HS_GCCFG_VBUSASEN (1 << 18)
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/* Bit 17 - Reserved */
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#define OTG_HS_GCCFG_PWRDWN (1 << 16)
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/* Bits 15:0 - Reserved */
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/* Device-mode CSRs */
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/* OTG_FS device control register (OTG_HS_DCTL) */
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/* Bits 31:12 - Reserved */
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#define OTG_HS_DCTL_POPRGDNE (1 << 11)
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#define OTG_HS_DCTL_CGONAK (1 << 10)
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#define OTG_HS_DCTL_SGONAK (1 << 9)
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#define OTG_HS_DCTL_SGINAK (1 << 8)
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#define OTG_HS_DCTL_TCTL_MASK (7 << 4)
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#define OTG_HS_DCTL_GONSTS (1 << 3)
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#define OTG_HS_DCTL_GINSTS (1 << 2)
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#define OTG_HS_DCTL_SDIS (1 << 1)
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#define OTG_HS_DCTL_RWUSIG (1 << 0)
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/* OTG_FS device configuration register (OTG_HS_DCFG) */
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#define OTG_HS_DCFG_DSPD 0x0003
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#define OTG_HS_DCFG_NZLSOHSK 0x0004
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#define OTG_HS_DCFG_DAD 0x07F0
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#define OTG_HS_DCFG_PFIVL 0x1800
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/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_HS_DIEPMSK) */
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/* Bits 31:10 - Reserved */
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#define OTG_HS_DIEPMSK_BIM (1 << 9)
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#define OTG_HS_DIEPMSK_TXFURM (1 << 8)
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/* Bit 7 - Reserved */
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#define OTG_HS_DIEPMSK_INEPNEM (1 << 6)
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#define OTG_HS_DIEPMSK_INEPNMM (1 << 5)
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#define OTG_HS_DIEPMSK_ITTXFEMSK (1 << 4)
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#define OTG_HS_DIEPMSK_TOM (1 << 3)
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/* Bit 2 - Reserved */
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#define OTG_HS_DIEPMSK_EPDM (1 << 1)
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#define OTG_HS_DIEPMSK_XFRCM (1 << 0)
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/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_HS_DOEPMSK) */
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/* Bits 31:10 - Reserved */
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#define OTG_HS_DOEPMSK_BOIM (1 << 9)
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#define OTG_HS_DOEPMSK_OPEM (1 << 8)
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/* Bit 7 - Reserved */
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#define OTG_HS_DOEPMSK_B2BSTUP (1 << 6)
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/* Bit 5 - Reserved */
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#define OTG_HS_DOEPMSK_OTEPDM (1 << 4)
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#define OTG_HS_DOEPMSK_STUPM (1 << 3)
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/* Bit 2 - Reserved */
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#define OTG_HS_DOEPMSK_EPDM (1 << 1)
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#define OTG_HS_DOEPMSK_XFRCM (1 << 0)
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/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_HS_DIEPCTL0) */
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#define OTG_HS_DIEPCTL0_EPENA (1 << 31)
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#define OTG_HS_DIEPCTL0_EPDIS (1 << 30)
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/* Bits 29:28 - Reserved */
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#define OTG_HS_DIEPCTLX_SD0PID (1 << 28)
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#define OTG_HS_DIEPCTL0_SNAK (1 << 27)
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#define OTG_HS_DIEPCTL0_CNAK (1 << 26)
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#define OTG_HS_DIEPCTL0_TXFNUM_MASK (0xf << 22)
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#define OTG_HS_DIEPCTL0_STALL (1 << 21)
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/* Bit 20 - Reserved */
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#define OTG_HS_DIEPCTL0_EPTYP_MASK (0x3 << 18)
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#define OTG_HS_DIEPCTL0_NAKSTS (1 << 17)
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/* Bit 16 - Reserved */
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#define OTG_HS_DIEPCTL0_USBAEP (1 << 15)
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/* Bits 14:2 - Reserved */
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#define OTG_HS_DIEPCTL0_MPSIZ_MASK (0x3 << 0)
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#define OTG_HS_DIEPCTL0_MPSIZ_64 (0x0 << 0)
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#define OTG_HS_DIEPCTL0_MPSIZ_32 (0x1 << 0)
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#define OTG_HS_DIEPCTL0_MPSIZ_16 (0x2 << 0)
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#define OTG_HS_DIEPCTL0_MPSIZ_8 (0x3 << 0)
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/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_HS_DOEPCTL0) */
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#define OTG_HS_DOEPCTL0_EPENA (1 << 31)
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#define OTG_HS_DOEPCTL0_EPDIS (1 << 30)
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/* Bits 29:28 - Reserved */
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#define OTG_HS_DOEPCTLX_SD0PID (1 << 28)
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#define OTG_HS_DOEPCTL0_SNAK (1 << 27)
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#define OTG_HS_DOEPCTL0_CNAK (1 << 26)
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/* Bits 25:22 - Reserved */
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#define OTG_HS_DOEPCTL0_STALL (1 << 21)
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#define OTG_HS_DOEPCTL0_SNPM (1 << 20)
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#define OTG_HS_DOEPCTL0_EPTYP_MASK (0x3 << 18)
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#define OTG_HS_DOEPCTL0_NAKSTS (1 << 17)
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/* Bit 16 - Reserved */
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#define OTG_HS_DOEPCTL0_USBAEP (1 << 15)
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/* Bits 14:2 - Reserved */
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#define OTG_HS_DOEPCTL0_MPSIZ_MASK (0x3 << 0)
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#define OTG_HS_DOEPCTL0_MPSIZ_64 (0x0 << 0)
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#define OTG_HS_DOEPCTL0_MPSIZ_32 (0x1 << 0)
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#define OTG_HS_DOEPCTL0_MPSIZ_16 (0x2 << 0)
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#define OTG_HS_DOEPCTL0_MPSIZ_8 (0x3 << 0)
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/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DIEPINTx) */
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/* Bits 31:8 - Reserved */
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#define OTG_HS_DIEPINTX_TXFE (1 << 7)
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#define OTG_HS_DIEPINTX_INEPNE (1 << 6)
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/* Bit 5 - Reserved */
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#define OTG_HS_DIEPINTX_ITTXFE (1 << 4)
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#define OTG_HS_DIEPINTX_TOC (1 << 3)
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/* Bit 2 - Reserved */
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#define OTG_HS_DIEPINTX_EPDISD (1 << 1)
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#define OTG_HS_DIEPINTX_XFRC (1 << 0)
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/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DOEPINTx) */
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/* Bits 31:7 - Reserved */
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#define OTG_HS_DOEPINTX_B2BSTUP (1 << 6)
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/* Bit 5 - Reserved */
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#define OTG_HS_DOEPINTX_OTEPDIS (1 << 4)
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#define OTG_HS_DOEPINTX_STUP (1 << 3)
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/* Bit 2 - Reserved */
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#define OTG_HS_DOEPINTX_EPDISD (1 << 1)
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#define OTG_HS_DOEPINTX_XFRC (1 << 0)
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/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_HS_DOEPTSIZ0) */
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/* Bit 31 - Reserved */
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#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
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#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)
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#define OTG_HS_DIEPSIZ0_STUPCNT_3 (0x3 << 29)
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#define OTG_HS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29)
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/* Bits 28:20 - Reserved */
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#define OTG_HS_DIEPSIZ0_PKTCNT (1 << 19)
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/* Bits 18:7 - Reserved */
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#define OTG_HS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0)
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#endif
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