7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/sam/pmc.h>
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#include <libopencm3/sam/eefc.h>
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/** Default peripheral clock frequency after reset. */
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u32 pmc_mck_frequency = 4000000;
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void pmc_xtal_enable(bool en, u8 startup_time)
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{
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if (en) {
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CKGR_MOR = (CKGR_MOR & ~CKGR_MOR_MOSCXTST_MASK) |
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CKGR_MOR_KEY | CKGR_MOR_MOSCXTEN |
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(startup_time << 8);
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while (!(PMC_SR & PMC_SR_MOSCXTS));
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} else {
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CKGR_MOR = CKGR_MOR_KEY | (CKGR_MOR & ~CKGR_MOR_MOSCXTEN);
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}
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}
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void pmc_plla_config(u8 mul, u8 div)
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{
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CKGR_PLLAR = CKGR_PLLAR_ONE | ((mul - 1) << 16) |
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CKGR_PLLAR_PLLACOUNT_MASK | div;
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while (!(PMC_SR & PMC_SR_LOCKA));
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}
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void pmc_peripheral_clock_enable(u8 pid)
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{
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if (pid < 32) {
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PMC_PCER0 = 1 << pid;
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} else {
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PMC_PCER1 = 1 << (pid & 31);
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}
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}
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void pmc_peripheral_clock_disable(u8 pid)
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{
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if (pid < 32) {
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PMC_PCDR0 = 1 << pid;
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} else {
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PMC_PCDR1 = 1 << (pid & 31);
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}
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}
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void pmc_mck_set_source(enum mck_src src)
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{
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PMC_MCKR = (PMC_MCKR & ~PMC_MCKR_CSS_MASK) | src;
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while (!(PMC_SR & PMC_SR_MCKRDY));
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}
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void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void)
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{
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eefc_set_latency(4);
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/* 12MHz external xtal, maximum possible startup time */
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pmc_xtal_enable(true, 0xff);
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/* Select as main oscillator */
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CKGR_MOR |= CKGR_MOR_KEY | CKGR_MOR_MOSCSEL;
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/* Multiply by 7 for 84MHz */
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pmc_plla_config(7, 1);
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pmc_mck_set_source(MCK_SRC_PLLA);
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pmc_mck_frequency = 84000000;
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}
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void pmc_clock_setup_in_rc_4mhz_out_84mhz(void)
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{
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eefc_set_latency(4);
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/* Select as main oscillator */
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CKGR_MOR = CKGR_MOR_KEY |
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(CKGR_MOR & ~(CKGR_MOR_MOSCSEL | CKGR_MOR_MOSCRCF_MASK));
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/* Multiply by 21 for 84MHz */
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pmc_plla_config(21, 1);
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pmc_mck_set_source(MCK_SRC_PLLA);
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pmc_mck_frequency = 84000000;
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}
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