7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
150 lines
4.5 KiB
C
150 lines
4.5 KiB
C
/** @addtogroup iwdg_file
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
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This library supports the Independent Watchdog Timer System in the STM32F1xx
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series of ARM Cortex Microcontrollers by ST Microelectronics.
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The watchdog timer uses the LSI (low speed internal) clock which is low power
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and continues to operate during stop and standby modes. Its frequency is
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nominally 32kHz (40kHz for the STM32F1xx series) but can vary from as low
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as 17kHz up to 60kHz (refer to datasheet electrical characteristics).
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Note that the User Configuration option byte provides a means of automatically
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enabling the IWDG timer at power on (with counter value 0xFFF). If the
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relevant bit is not set, the IWDG timer must be enabled by software.
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@note: Tested: CPU STM32F103RET6, Board ET-ARM Stamp STM32
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/iwdg.h>
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#define LSI_FREQUENCY 32000
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#define COUNT_LENGTH 12
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#define COUNT_MASK ((1 << COUNT_LENGTH)-1)
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/*---------------------------------------------------------------------------*/
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/** @brief IWDG Enable Watchdog Timer
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The watchdog timer is started. The timeout period defaults to 512 milliseconds
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unless it has been previously defined.
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*/
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void iwdg_start(void)
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{
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IWDG_KR = IWDG_KR_START;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief IWDG Set Period in Milliseconds
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The countdown period is converted into count and prescale values. The maximum
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period is 32.76 seconds; values above this are truncated. Periods less than 1ms
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are not supported by this library.
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A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
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can occasionally occur if the prescale or preload registers are currently busy
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loading a previous value.
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@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset
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until a system reset is issued.
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*/
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void iwdg_set_period_ms(u32 period)
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{
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u32 count, prescale, reload, exponent;
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/* Set the count to represent ticks of the 32kHz LSI clock */
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count = (period << 5);
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/* Strip off the first 12 bits to get the prescale value required */
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prescale = (count >> 12);
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if (prescale > 256) {
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exponent = IWDG_PR_DIV256; reload = COUNT_MASK;
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} else if (prescale > 128) {
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exponent = IWDG_PR_DIV256; reload = (count >> 8);
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} else if (prescale > 64) {
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exponent = IWDG_PR_DIV128; reload = (count >> 7);
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} else if (prescale > 32) {
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exponent = IWDG_PR_DIV64; reload = (count >> 6);
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} else if (prescale > 16) {
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exponent = IWDG_PR_DIV32; reload = (count >> 5);
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} else if (prescale > 8) {
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exponent = IWDG_PR_DIV16; reload = (count >> 4);
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} else if (prescale > 4) {
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exponent = IWDG_PR_DIV8; reload = (count >> 3);
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} else {
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exponent = IWDG_PR_DIV4; reload = (count >> 2);
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}
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/* Avoid the undefined situation of a zero count */
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if (count == 0) {
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count = 1;
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}
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while (iwdg_prescaler_busy());
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IWDG_KR = IWDG_KR_UNLOCK;
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IWDG_PR = exponent;
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while (iwdg_reload_busy());
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IWDG_KR = IWDG_KR_UNLOCK;
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IWDG_RLR = (reload & COUNT_MASK);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief IWDG Get Reload Register Status
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@returns boolean: TRUE if the reload register is busy and unavailable for
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loading a new count value.
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*/
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bool iwdg_reload_busy(void)
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{
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return IWDG_SR & IWDG_SR_RVU;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief IWDG Get Prescaler Register Status
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@returns boolean: TRUE if the prescaler register is busy and unavailable for
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loading a new period value.
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*/
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bool iwdg_prescaler_busy(void)
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{
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return IWDG_SR & IWDG_SR_PVU;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief IWDG reset Watchdog Timer
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The watchdog timer is reset. The counter restarts from the value in the reload
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register.
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*/
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void iwdg_reset(void)
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{
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IWDG_KR = IWDG_KR_RESET;
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}
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/**@}*/
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