7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
124 lines
3.4 KiB
C
124 lines
3.4 KiB
C
/** @addtogroup rtc_file
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@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/rtc.h>
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/*---------------------------------------------------------------------------*/
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/** @brief Set RTC prescalars.
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This sets the RTC synchronous and asynchronous prescalars.
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*/
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void rtc_set_prescaler(u32 sync, u32 async)
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{
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/*
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* Even if only one of the two fields needs to be changed,
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* 2 separate write accesses must be performed to the RTC_PRER register.
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*/
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RTC_PRER = (sync & RTC_PRER_PREDIV_S_MASK);
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RTC_PRER |= (async << RTC_PRER_PREDIV_A_SHIFT);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Wait for RTC registers to be synchronised with the APB1 bus
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Time and Date are accessed through shadow registers which must be synchronized
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*/
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void rtc_wait_for_synchro(void)
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{
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/* Unlock RTC registers */
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RTC_WPR = 0xca;
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RTC_WPR = 0x53;
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RTC_ISR &= ~(RTC_ISR_RSF);
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while (!(RTC_ISR & RTC_ISR_RSF));
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/* disable write protection again */
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RTC_WPR = 0xff;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Unlock write access to the RTC registers
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*/
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void rtc_unlock(void)
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{
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RTC_WPR = 0xca;
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RTC_WPR = 0x53;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Lock write access to the RTC registers
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*/
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void rtc_lock(void)
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{
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RTC_WPR = 0xff;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Sets the wakeup time auto-reload value
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*/
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void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel)
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{
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/* FTFM:
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* The following sequence is required to configure or change the wakeup
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* timer auto-reload value (WUT[15:0] in RTC_WUTR):
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* 1. Clear WUTE in RTC_CR to disable the wakeup timer.
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*/
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RTC_CR &= ~RTC_CR_WUTE;
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/* 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to
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* wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed.
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* It takes around 2 RTCCLK clock cycles (due to clock
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* synchronization).
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*/
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while (!((RTC_ISR) & (RTC_ISR_WUTWF)));
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/* 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup
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* clock selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR
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* to enable the timer again. The wakeup timer restarts
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* down-counting.
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*/
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RTC_WUTR = wkup_time;
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RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT);
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RTC_CR |= RTC_CR_WUTE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clears the wakeup flag
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@details This function should be called first in the rtc_wkup_isr()
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*/
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void rtc_clear_wakeup_flag(void)
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{
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RTC_ISR &= ~RTC_ISR_WUTF;
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}
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/**@}*/
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