Onno Kortmann 868d65d872 STM32F0: Turn on PLL clock source when asked to ...

The STM32F05xxx/06xxx manual describes on p.98 (Sec 7.4.1) the RCC_CR
register, on which it says that bit 24 is the PLLON bit which has to be
enabled before using the PLL. This causes the PLL to be enabled with
rcc_osc_on(PLL).

2013-12-16 19:37:06 +00:00

..

common

[timers] Fixed typo

2013-11-08 16:00:51 -07:00

f0

STM32F0: Turn on PLL clock source when asked to

2013-12-16 19:37:06 +00:00

f1

Fix the order of ADC injected channel list

2013-12-04 22:03:23 +00:00

f2

[stm32] Unify f0/f3 SPI and correct all makefiles

2013-11-07 21:50:48 +00:00

f3

Fix the order of ADC injected channel list

2013-12-04 22:03:23 +00:00

f4

Fix the order of ADC injected channel list

2013-12-04 22:03:23 +00:00

l1

[stm32] Unify f0/f3 SPI and correct all makefiles

2013-11-07 21:50:48 +00:00

can.c

Stile fixes run, 80 char boundry.

2013-06-12 21:07:35 -07:00

desig.c

[stm32] Use correct offsets for UniqueID bits

2013-10-15 11:16:14 +00:00