904345eaf1
Reserved bits are marked explicitly in the comments. ASCR defines are changed to be consistent with the reference manual. HYSCR, ASMR, CMR and CICR register defines are rewritten to be more concise and readable.
387 lines
13 KiB
C
387 lines
13 KiB
C
/** @defgroup ri_defines Routing Interface registers
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*
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* @brief <b>Register definitions for the STM32L1xx Routing Interface</b>
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*
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* @ingroup STM32L1xx
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2016 Marek Koza <qyx@krtko.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*
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* Based on the RM0038 Reference manual
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* (STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM®-based
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* 32-bit MCUs)
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*/
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/**@{*/
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/*
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* There is a mismatch in the RM0038 in the RI register offset addresses (they
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* are relative to the COMP base address instead of the RI base address for an
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* unknown reason). We are subtracting 4 in order to use them with ROUTING_BASE.
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*/
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#define RI_BASE ROUTING_BASE - 0x04
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#define RI_ICR MMIO32(RI_BASE + 0x04)
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#define RI_ASCR1 MMIO32(RI_BASE + 0x08)
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#define RI_ASCR2 MMIO32(RI_BASE + 0x0c)
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#define RI_HYSCR1 MMIO32(RI_BASE + 0x10)
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#define RI_HYSCR2 MMIO32(RI_BASE + 0x14)
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#define RI_HYSCR3 MMIO32(RI_BASE + 0x18)
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#define RI_HYSCR4 MMIO32(RI_BASE + 0x1c)
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#define RI_ASMR1 MMIO32(RI_BASE + 0x20)
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#define RI_CMR1 MMIO32(RI_BASE + 0x24)
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#define RI_CICR1 MMIO32(RI_BASE + 0x28)
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#define RI_ASMR2 MMIO32(RI_BASE + 0x2c)
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#define RI_CMR2 MMIO32(RI_BASE + 0x30)
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#define RI_CICR2 MMIO32(RI_BASE + 0x34)
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#define RI_ASMR3 MMIO32(RI_BASE + 0x38)
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#define RI_CMR3 MMIO32(RI_BASE + 0x3c)
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#define RI_CICR3 MMIO32(RI_BASE + 0x40)
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#define RI_ASMR4 MMIO32(RI_BASE + 0x44)
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#define RI_CMR4 MMIO32(RI_BASE + 0x48)
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#define RI_CICR4 MMIO32(RI_BASE + 0x4c)
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#define RI_ASMR5 MMIO32(RI_BASE + 0x50)
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#define RI_CMR5 MMIO32(RI_BASE + 0x54)
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#define RI_CICR5 MMIO32(RI_BASE + 0x58)
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/**
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* RI input capture register
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*
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* The RI_ICR register is used to select the routing of 4 full ports to the
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* input captures of TIM2, TIM3 and TIM4.
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*/
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#define RI_ICR_IC1IOS_SHIFT 0
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#define RI_ICR_IC1IOS_MASK 0xf
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#define RI_ICR_IC2IOS_SHIFT 4
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#define RI_ICR_IC2IOS_MASK 0xf
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#define RI_ICR_IC3IOS_SHIFT 8
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#define RI_ICR_IC3IOS_MASK 0xf
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#define RI_ICR_IC4IOS_SHIFT 12
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#define RI_ICR_IC4IOS_MASK 0xf
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#define RI_ICR_TIM_SHIFT 16
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#define RI_ICR_TIM_MASK 0x3
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#define RI_ICR_IC1 (1 << 18)
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#define RI_ICR_IC2 (1 << 19)
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#define RI_ICR_IC3 (1 << 20)
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#define RI_ICR_IC4 (1 << 21)
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/* bits 22-31 reserved */
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/**
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* RI analog switches control register 1
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*
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* The RI_ASCR1 register is used to configure the analog switches of the I/Os
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* linked to the ADC. These I/Os are pointed to by the ADC channel number.
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*/
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#define RI_ASCR1_CH0_GR1_1 (1 << 0)
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#define RI_ASCR1_CH1_GR1_2 (1 << 1)
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#define RI_ASCR1_CH2_GR1_3 (1 << 2)
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#define RI_ASCR1_CH3_GR1_4 (1 << 3)
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#define RI_ASCR1_CH4 (1 << 4)
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#define RI_ASCR1_CH5 (1 << 5)
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#define RI_ASCR1_CH6_GR2_1 (1 << 6)
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#define RI_ASCR1_CH7_GR2_2 (1 << 7)
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#define RI_ASCR1_CH8_GR3_1 (1 << 8)
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#define RI_ASCR1_CH9_GR3_2 (1 << 9)
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#define RI_ASCR1_CH10_GR8_1 (1 << 10)
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#define RI_ASCR1_CH11_GR8_2 (1 << 11)
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#define RI_ASCR1_CH12_GR8_3 (1 << 12)
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#define RI_ASCR1_CH13_GR8_4 (1 << 13)
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#define RI_ASCR1_CH14_GR9_1 (1 << 14)
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#define RI_ASCR1_CH15_GR9_2 (1 << 15)
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#define RI_ASCR1_CH31_GR11_5 (1 << 16)
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/* bit 17 reserved */
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#define RI_ASCR1_CH18_GR7_1 (1 << 18)
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#define RI_ASCR1_CH19_GR7_2 (1 << 19)
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#define RI_ASCR1_CH20_GR7_3 (1 << 20)
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#define RI_ASCR1_CH21_GR7_4 (1 << 21)
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#define RI_ASCR1_CH22 (1 << 22)
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#define RI_ASCR1_CH23 (1 << 23)
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#define RI_ASCR1_CH24 (1 << 24)
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#define RI_ASCR1_CH25 (1 << 25)
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#define RI_ASCR1_VCOMP (1 << 26)
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#define RI_ASCR1_CH27_GR11_1 (1 << 27)
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#define RI_ASCR1_CH28_GR11_2 (1 << 28)
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#define RI_ASCR1_CH29_GR11_3 (1 << 29)
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#define RI_ASCR1_CH30_GR11_4 (1 << 30)
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#define RI_ASCR1_SCM (1 << 31)
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/**
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* RI analog switches control register 2
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*
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* The RI_ASCR2 register is used to configure the analog switches of groups of
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* I/Os not linked to the ADC. In this way, predefined groups of I/Os can be
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* connected together.
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*/
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#define RI_ASCR2_GR10_1 (1 << 0)
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#define RI_ASCR2_GR10_2 (1 << 1)
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#define RI_ASCR2_GR10_3 (1 << 2)
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#define RI_ASCR2_GR10_4 (1 << 3)
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#define RI_ASCR2_GR6_1 (1 << 4)
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#define RI_ASCR2_GR6_2 (1 << 5)
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#define RI_ASCR2_GR5_1 (1 << 6)
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#define RI_ASCR2_GR5_2 (1 << 7)
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#define RI_ASCR2_GR5_3 (1 << 8)
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#define RI_ASCR2_GR4_1 (1 << 9)
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#define RI_ASCR2_GR4_2 (1 << 10)
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#define RI_ASCR2_GR4_3 (1 << 11)
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/* bits 12-15 reserved */
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#define RI_ASCR2_CH0B_GR3_3 (1 << 16)
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#define RI_ASCR2_CH1B_GR3_4 (1 << 17)
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#define RI_ASCR2_CH2B_GR3_5 (1 << 18)
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#define RI_ASCR2_CH3B_GR9_3 (1 << 19)
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#define RI_ASCR2_CH6B_GR9_4 (1 << 20)
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#define RI_ASCR2_CH7B_GR2_3 (1 << 21)
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#define RI_ASCR2_CH8B_GR2_4 (1 << 22)
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#define RI_ASCR2_CH9B_GR2_5 (1 << 23)
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#define RI_ASCR2_CH10B_GR7_5 (1 << 24)
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#define RI_ASCR2_CH11B_GR7_6 (1 << 25)
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#define RI_ASCR2_CH12B_GR7_7 (1 << 26)
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#define RI_ASCR2_GR6_3 (1 << 27)
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#define RI_ASCR2_GR6_4 (1 << 28)
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/* bits 29-31 reserved */
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/**
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* RI hysteresis control register 1
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*
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* The RI_HYSCR1 register is used to enable/disable the hysteresis of the input
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* Schmitt trigger of ports A and B.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_HYSCR1_PA(x) (x)
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#define RI_HYSCR1_PB(x) (x << 16)
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/**
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* RI hysteresis control register 2
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*
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* RI_HYSCR2 register allows to enable/disable hysteresis of input Schmitt
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* trigger of ports C and D.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_HYSCR2_PC(x) (x)
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#define RI_HYSCR2_PD(x) (x << 16)
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/**
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* RI hysteresis control register 3
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*
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* The RI_HYSCR3 register is used to enable/disable the hysteresis of the input
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* Schmitt trigger of the entire port E and F.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_HYSCR3_PE(x) (x)
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#define RI_HYSCR3_PF(x) (x << 16)
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/**
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* RI hysteresis control register 4
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*
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* The RI_HYSCR4 register is used to enable/disable the hysteresis of the input
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* Schmitt trigger of the entire port G.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_HYSCR2_PG(x) (x)
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/* bits 16-31 reserved */
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/**
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* Analog switch mode register (RI_ASMR1)
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*
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* The RI_ASMR1 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used to select if analog switches of port A are to be controlled
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* by the timer OC or through the ADC interface or RI_ASCRx registers.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_ASMR1_PA(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel mask register (RI_CMR1)
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*
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* RI_CMR1 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is
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* used to mask a port A channel designated as a timer input capture (after
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* acquisition completion to avoid triggering multiple detections).
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CMR1_PA(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel identification for capture register (RI_CICR1)
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*
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* The RI_CICR1 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used when analog switches are controlled by a timer OC. RI_CICR1
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* allows a channel to be identified for timer input capture.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CICR1_PA(x) (x)
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/* bits 16-31 reserved */
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/**
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* Analog switch mode register (RI_ASMR2)
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*
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* The RI_ASMR2 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used to select if analog switches of port B are to be controlled
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* by the timer OC or through the ADC interface or RI_ASCRx registers.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_ASMR2_PB(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel mask register (RI_CMR2)
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*
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* RI_CMR2 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is
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* used to mask a port B channel designated as a timer input capture (after
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* acquisition completion to avoid triggering multiple detections).
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CMR2_PB(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel identification for capture register (RI_CICR2)
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*
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* The RI_CICR2 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used when analog switches are controlled by a timer OC. RI_CICR2
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* allows a channel to be identified for timer input capture.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CICR2_PB(x) (x)
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/* bits 16-31 reserved */
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/**
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* Analog switch mode register (RI_ASMR3)
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*
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* The RI_ASMR3 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used to select if analog switches of port C are to be controlled
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* by the timer OC or through the ADC interface or RI_ASCRx registers.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_ASMR3_PC(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel mask register (RI_CMR3)
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*
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* RI_CMR3 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is
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* used to mask a port C channel designated as a timer input capture (after
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* acquisition completion to avoid triggering multiple detections).
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CMR3_PC(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel identification for capture register (RI_CICR3)
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*
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* The RI_CICR3 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used when analog switches are controlled by a timer OC. RI_CICR3
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* allows a channel to be identified for timer input capture.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CICR3_PC(x) (x)
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/* bits 16-31 reserved */
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/**
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* Analog switch mode register (RI_ASMR4)
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*
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* The RI_ASMR4 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used to select if analog switches of port F are to be controlled
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* by the timer OC or through the ADC interface or RI_ASCRx registers.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_ASMR4_PF(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel mask register (RI_CMRF)
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*
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* RI_CMR4 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is
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* used to mask a port F channel designated as a timer input capture (after
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* acquisition completion to avoid triggering multiple detections).
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CMR4_PF(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel identification for capture register (RI_CICR4)
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*
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* The RI_CICR4 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used when analog switches are controlled by a timer OC. RI_CICR4
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* allows a channel to be identified for timer input capture.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CICR4_PF(x) (x)
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/* bits 16-31 reserved */
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/**
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* Analog switch mode register (RI_ASMR5)
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*
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* The RI_ASMR5 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used to select if analog switches of port G are to be controlled
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* by the timer OC or through the ADC interface or RI_ASCRx registers.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_ASMR5_PG(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel mask register (RI_CMR5)
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*
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* RI_CMR1 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is
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* used to mask a port G channel designated as a timer input capture (after
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* acquisition completion to avoid triggering multiple detections).
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CMR5_PG(x) (x)
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/* bits 16-31 reserved */
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/**
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* Channel identification for capture register (RI_CICR5)
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*
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* The RI_CICR5 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices
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* only and is used when analog switches are controlled by a timer OC. RI_CICR5
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* allows a channel to be identified for timer input capture.
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*
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* GPIO0-GPIO15 defines should be used as parameters.
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*/
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#define RI_CICR5_PG(x) (x)
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/* bits 16-31 reserved */
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/**@}*/
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