3c6e9fd56d
So that the navigation pane works correctly in browsers. Some additional doc fixes put in where found (but many more still to go). Added some dummy .c and .h files to bring the associated docs into line. makefile changed to allow 'make html' as well as 'make doc' (the latter only does html anyway).
163 lines
5.6 KiB
C
163 lines
5.6 KiB
C
/** @defgroup tsc_defines TSC Defines
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*
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* @brief <b>Defined Constants and Types for the STM32F0xx Touch Sensor</b>
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*
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* @ingroup STM32F0xx_defines
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*
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* @version 1.0.0
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*
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* @date 11 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_TSC_H
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#define LIBOPENCM3_TSC_H
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/**@{*/
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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/*****************************************************************************/
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/* Module definitions */
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/*****************************************************************************/
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#define TSC TSC_BASE
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/*****************************************************************************/
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/* Register definitions */
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/*****************************************************************************/
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#define TSC_CR MMIO32(TSC_BASE + 0x00)
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#define TSC_IER MMIO32(TSC_BASE + 0x04)
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#define TSC_ICR MMIO32(TSC_BASE + 0x08)
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#define TSC_ISR MMIO32(TSC_BASE + 0x0c)
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#define TSC_IOHCR MMIO32(TSC_BASE + 0x10)
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#define TSC_IOASCR MMIO32(TSC_BASE + 0x18)
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#define TSC_IOSCR MMIO32(TSC_BASE + 0x20)
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#define TSC_IOCCR MMIO32(TSC_BASE + 0x28)
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#define TSC_IOGCSR MMIO32(TSC_BASE + 0x30)
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#define TSC_IOGxCR(x) MMIO8(TSC_BASE + 0x34 + (x)*4)
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/*****************************************************************************/
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/* Register values */
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/*****************************************************************************/
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/* TSC_CR Values ------------------------------------------------------------*/
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#define TSC_CR_CTPH_SHIFT 28
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#define TSC_CR_CTPH (0xF << TSC_CR_CTPH_SHIFT)
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#define TSC_CR_CTPL_SHIFT 24
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#define TSC_CR_CTPL (0x0F << TSC_CR_CTPL_SHIFT)
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#define TSC_CR_SSD_SHIFT 17
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#define TSC_CR_SSD (0x7F << TSC_CR_SSD_SHIFT)
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#define TSC_CR_SSE (1 << 16)
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#define TSC_CR_SSPSC (1 << 15)
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#define TSC_CR_PGPSC_SHIFT 12
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#define TSC_CR_PGPSC (7 << TSC_CR_PGPSC_SHIFT)
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#define TSC_CR_MCV_SHIFT 5
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#define TSC_CR_MCV (7 << TSC_CR_MCV_SHIFT)
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#define TSC_CR_IODEF (1 << 4)
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#define TSC_CR_SYNCPOL (1 << 3)
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#define TSC_CR_AM (1 << 2)
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#define TSC_CR_START (1 << 1)
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#define TSC_CR_TSCE (1 << 0)
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/* TSC_IER Values -----------------------------------------------------------*/
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#define TSC_IER_MCEIE (1 << 1)
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#define TSC_IER_EOAIE (1 << 0)
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/* TSC_ICR Values -----------------------------------------------------------*/
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#define TSC_ICR_MCEIC (1 << 1)
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#define TSC_ICR_EOAIC (1 << 0)
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/* TSC_ISR Values -----------------------------------------------------------*/
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#define TSC_ISR_MCEF (1 << 1)
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#define TSC_ISR_EOAF (1 << 0)
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/* TSC_IOHCR Values ---------------------------------------------------------*/
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/* Bit helper g = [1..6] io = [1..4] */
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#define TSC_IOBIT_VAL(g, io) ((1 << ((io)-1)) << (((g)-1)*4))
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#define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1, io)
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#define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2, io)
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#define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3, io)
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#define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4, io)
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#define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5, io)
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#define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6, io)
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/* TSC_IOASCR Values --------------------------------------------------------*/
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#define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1, io)
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#define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2, io)
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#define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3, io)
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#define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4, io)
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#define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5, io)
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#define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6, io)
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/* TSC_IOSCR Values ---------------------------------------------------------*/
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#define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1, io)
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#define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2, io)
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#define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3, io)
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#define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4, io)
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#define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5, io)
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#define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6, io)
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/* TSC_IOCCR Values ---------------------------------------------------------*/
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#define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1, io)
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#define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2, io)
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#define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3, io)
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#define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4, io)
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#define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5, io)
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#define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6, io)
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/* TSC_IOGCSR Values --------------------------------------------------------*/
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#define TSC_IOGCSR_GxE(x) (1 << ((x)-1))
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#define TSC_IOGCSR_GxS(x) (1 << ((x)+15))
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/*****************************************************************************/
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/* API definitions */
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/*****************************************************************************/
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/*****************************************************************************/
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/* API Functions */
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/*****************************************************************************/
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BEGIN_DECLS
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END_DECLS
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/**@}*/
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#endif
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