Marcus Hultmark Varejao 6e87892a7e stm32f4: rcc: fix setup of main system clock with pllp
Fixes: 57c2b00a69f97205313e1c7ab8116ee1893b231e

There was an issue with the pllp value calculation where the masking was done
in the wrong place. The pllp value was always equivalent to 2 (the bits were
always set to 0b00) which could result in an undesired system clock frequency.
2016-09-02 10:33:27 +02:00
..
2015-02-12 19:02:51 -08:00