acc276a612
In adc.h additional defines needed to assist documentation - lines 172-191 added, and 384,436-451 are duplicates of earlier defines to complete parameter sets (compiler has no trouble with these). Minor doc corrections to other files. No code changes (apart from additional defines).
132 lines
3.9 KiB
C
132 lines
3.9 KiB
C
/** @defgroup STM32F_nvic_defines NVIC Defines
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@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
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@ingroup STM32F_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
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@date 18 August 2012
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_NVIC_H
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#define LIBOPENCM3_NVIC_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- NVIC Registers ------------------------------------------------------ */
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/* ISER: Interrupt Set Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
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/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
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/* ICER: Interrupt Clear Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
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/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
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/* ISPR: Interrupt Set Pending Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
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/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
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/* ICPR: Interrupt Clear Pending Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
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/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
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/* IABR: Interrupt Active Bit Register */
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/* Note: 8 32bit Registers */
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#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
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/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
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/* IPR: Interrupt Priority Registers */
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/* Note: 240 8bit Registers */
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#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
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/* STIR: Software Trigger Interrupt Register */
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#define NVIC_STIR MMIO32(STIR_BASE)
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/* --- IRQ channel numbers-------------------------------------------------- */
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/* Cortex M3 System Interrupts */
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/** @defgroup nvic_sysint Cortex M3 System Interrupts
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@ingroup STM32F_nvic_defines
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IRQ numbers -3 and -6 to -9 are reserved
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@{*/
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#define NVIC_NMI_IRQ -14
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#define NVIC_HARD_FAULT_IRQ -13
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#define NVIC_MEM_MANAGE_IRQ -12
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#define NVIC_BUS_FAULT_IRQ -11
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#define NVIC_USAGE_FAULT_IRQ -10
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/* irq numbers -6 to -9 are reserved */
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#define NVIC_SV_CALL_IRQ -5
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#define DEBUG_MONITOR_IRQ -4
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/* irq number -3 reserved */
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#define NVIC_PENDSV_IRQ -2
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#define NVIC_SYSTICK_IRQ -1
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/**@}*/
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/* Note: User interrupts are family specific and are defined in a family
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* specific header file in the corresponding subfolder.
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*/
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#if defined(STM32F1)
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# include <libopencm3/stm32/f1/nvic_f1.h>
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#elif defined(STM32F2)
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# include <libopencm3/stm32/f2/nvic_f2.h>
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#elif defined(STM32F4)
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# include <libopencm3/stm32/f4/nvic_f4.h>
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#else
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# error "stm32 family not defined."
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#endif
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/* --- NVIC functions ------------------------------------------------------ */
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void nvic_enable_irq(u8 irqn);
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void nvic_disable_irq(u8 irqn);
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u8 nvic_get_pending_irq(u8 irqn);
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void nvic_set_pending_irq(u8 irqn);
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void nvic_clear_pending_irq(u8 irqn);
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u8 nvic_get_active_irq(u8 irqn);
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u8 nvic_get_irq_enabled(u8 irqn);
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void nvic_set_priority(u8 irqn, u8 priority);
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void nvic_generate_software_interrupt(u16 irqn);
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#endif
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/**@}*/
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