70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
/** @defgroup pwr_defines PWR Defines
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*
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* @brief <b>Defined Constants and Types for the STM32F3xx Power control </b>
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*
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* @ingroup STM32F3xx_defines
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*
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* @author @htmlonly © @endhtmlonly 2011
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* Stephen Caudle <scaudle@doceme.com>
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* @author @htmlonly © @endhtmlonly 2013
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* Fernando Cortes <fernando.corcam@gmail.com>
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* @author @htmlonly © @endhtmlonly 2013
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* Guillermo Rivera <memogrg@gmail.com>
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*
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* @version 1.0.0
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*
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* @date 11 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
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* Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3)
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* Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3)
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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#include <libopencm3/stm32/common/pwr_common_v1.h>
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/* --- PWR_CR values ------------------------------------------------------- */
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/* Bits [31:10]: Reserved */
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#define PWR_CR_DBP (1 << 8)
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/* Bits [7:5]: Reserved PLS: PVD level selection. (Power Voltage Detector) */
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#define PWR_CR_PVDE (1 << 4)
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#define PWR_CR_CSBF (1 << 3)
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#define PWR_CR_CWUF (1 << 2)
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#define PWR_CR_PDDS (1 << 1)
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#define PWR_CR_LPDS (1 << 0)
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/* --- PWR_CSR values ------------------------------------------------------ */
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/* Bits [31:10]: Reserved */
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#define PWR_CSR_EWUP2 (1 << 9)
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#define PWR_CSR_EWUP1 (1 << 8)
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/* Bits [7:3]: Reserved */
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#define PWR_CSR_PVDO (1 << 2)
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#define PWR_CSR_SBF (1 << 1)
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#define PWR_CSR_WUF (1 << 0)
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#endif
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