2b1ddc8490
The original submitter of this squished everything into one series, and has not returned. The code mostly appears good, and review comments were followed for the most part. The project doesn't really maintain any testing or board farm for sam3/sam4 parts, so we're going to just trust our users. Reviewed-by: Karl Palsson <karlp@tweak.net.au> sam/4l: IRQ Configuration file (irq.json) sam/4l: Basic Memory Map. sam/4l: GPIO Defines. sam/4l: GPIO Functions Added everything that needed to compile the library: Makefile, Linker Script and common includes. sam/4l: SCIF function to start OSC. sam/4l: GPIO Enable/Disable and Multiplexing configuration functions. sam/4l: PLL Clock configuration. sam/4l: Peripheral clock configuration and basic USART support. sam: USART Character length configuration. sam/4l: Generic Clock configuration functions. sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
279 lines
7.7 KiB
C
279 lines
7.7 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PM_H
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#define LIBOPENCM3_PM_H
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#include <libopencm3/sam/memorymap.h>
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/* --- Power Manager (PM) registers ----------------------- */
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/* Main Clock Control MCCTRL Read/Write */
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#define PM_MCCTRL MMIO32(PM_BASE + 0x000)
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#define PM_MCCTRL_KEY (PM_UNLOCK_KEY)
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/* CPU & PBx Clock Select, Read/Write */
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#define PM_CKSEL(I) MMIO32(PM_BASE + 0x004 + (0x004 * (I)))
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#define PM_CKSEL_KEY(I) (PM_UNLOCK_KEY | (0x004 + (0x004 * (I))))
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#define PM_MASK(I) MMIO32(PM_BASE + 0x020 + (0x004) * (I))
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#define PM_MASK_KEY(I) (PM_UNLOCK_KEY | (0x020 + (0x004) * (I)))
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/* CPU Mask CPUMASK Read/Write */
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#define PM_CPUMASK MMIO32(PM_BASE + 0x020)
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/* HSB Mask HSBMASK Read/Write */
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#define PM_HSBMASK MMIO32(PM_BASE + 0x024)
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/* PBA Mask PBAMASK Read/Write */
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#define PM_PBAMASK MMIO32(PM_BASE + 0x028)
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#define PM_PBAMASK_KEY (PM_UNLOCK_KEY | 0x028)
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/* PBB Mask PBBMASK Read/Write */
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#define PM_PBBMASK MMIO32(PM_BASE + 0x02C)
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/* PBC Mask PBCMASK Read/Write */
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#define PM_PBCMASK MMIO32(PM_BASE + 0x030)
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/* PBD Mask PBDMASK Read/Write */
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#define PM_PBDMASK MMIO32(PM_BASE + 0x034)
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/* PBA Divided Mask PBADIVMASK Read/Write */
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#define PM_PBADIVMASK MMIO32(PM_BASE + 0x040)
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#define PM_PBADIVMASK_KEY (PM_UNLOCK_KEY | 0x040)
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/* Clock Failure Detector Control CFDCTRL Read/Write */
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#define PM_CFDCTRL MMIO32(PM_BASE + 0x054)
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/* Unlock Register UNLOCK Write-only */
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#define PM_UNLOCK MMIO32(PM_BASE + 0x058)
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#define PM_UNLOCK_KEY (0xAA << 24)
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/* Interrupt Enable Register IER Write-only */
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#define PM_IER MMIO32(PM_BASE + 0x0C0)
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/* Interrupt Disable Register IDR Write-only */
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#define PM_IDR MMIO32(PM_BASE + 0x0C4)
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/* Interrupt Mask Register IMR Read-only */
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#define PM_IMR MMIO32(PM_BASE + 0x0C8)
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/* Interrupt Status Register ISR Read-only */
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#define PM_ISR MMIO32(PM_BASE + 0x0CC)
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/* Interrupt Clear Register ICR Write-only */
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#define PM_ICR MMIO32(PM_BASE + 0x0D0)
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/* Status Register SR Read-only */
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#define PM_SR MMIO32(PM_BASE + 0x0D4)
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/* Peripheral Power Control Register PPCR Read/Write */
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#define PM_PPCR MMIO32(PM_BASE + 0x160)
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/* Reset Cause Register RCAUSE Read-only */
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#define PM_RCAUSE MMIO32(PM_BASE + 0x180)
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/* Wake Cause Register WCAUSE Read-only */
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#define PM_WCAUSE MMIO32(PM_BASE + 0x184)
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/* Asynchronous Wake Enable AWEN Read/Write */
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#define PM_AWEN MMIO32(PM_BASE + 0x188)
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/* Protection Control Register PROTCTRL Read/Write */
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#define PM_PROTCTRL MMIO32(PM_BASE + 0x18C)
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/* Fast Sleep Register FASTSLEEP Read/Write */
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#define PM_FASTSLEEP MMIO32(PM_BASE + 0x194)
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/* Configuration Register CONFIG Read-only */
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#define PM_CONFIG MMIO32(PM_BASE + 0x3F8)
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/* Version Register VERSION Read-only */
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#define PM_VERSION MMIO32(PM_BASE + 0x3FC)
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/* --- Register contents --------------------------------------------------- */
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#define PM_MCCTRL_MCSEL_SHIFT 0
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#define PM_MCCTRL_MCSEL_MASK 3
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// Values common for CPUSEL and PBxSEL
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#define PM_CKSEL_DIV (1 << 7)
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#define PM_CKSEL_MASK (3)
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#define PM_CPUMASK_OSC (1 << 0)
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#define PM_HSBMASK_PDCA (1 << 0)
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#define PM_HSBMASK_FLASHCALW (1 << 1)
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#define PM_HSBMASK_FLASHCALW_PICO (1 << 2)
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#define PM_HSBMASK_USBC (1 << 3)
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#define PM_HSBMASK_CRCCU (1 << 4)
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#define PM_HSBMASK_APBA (1 << 5)
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#define PM_HSBMASK_APBB (1 << 6)
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#define PM_HSBMASK_APBC (1 << 7)
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#define PM_HSBMASK_APBD (1 << 8)
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#define PM_HSBMASK_AESA (1 << 9)
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#define PM_PBAMASK_IISC (1 << 0)
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#define PM_PBAMASK_SPI (1 << 1)
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#define PM_PBAMASK_TC0 (1 << 2)
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#define PM_PBAMASK_TC1 (1 << 3)
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#define PM_PBAMASK_TWIM0 (1 << 4)
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#define PM_PBAMASK_TWIS0 (1 << 5)
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#define PM_PBAMASK_TWIM1 (1 << 6)
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#define PM_PBAMASK_TWIS1 (1 << 7)
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#define PM_PBAMASK_USART0 (1 << 8)
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#define PM_PBAMASK_USART1 (1 << 9)
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#define PM_PBAMASK_USART2 (1 << 10)
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#define PM_PBAMASK_USART3 (1 << 11)
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#define PM_PBAMASK_ADCIFE (1 << 12)
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#define PM_PBAMASK_DACC (1 << 13)
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#define PM_PBAMASK_ACIFC (1 << 14)
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#define PM_PBAMASK_GLOC (1 << 15)
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#define PM_PBAMASK_ABDACB (1 << 16)
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#define PM_PBAMASK_TRNG (1 << 17)
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#define PM_PBAMASK_PARC (1 << 18)
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#define PM_PBAMASK_CATB (1 << 19)
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/* -- */
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#define PM_PBAMASK_TWIM2 (1 << 21)
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#define PM_PBAMASK_TWIM3 (1 << 22)
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#define PM_PBAMASK_LCDCA (1 << 23)
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#define PM_PBBMASK_FLASHCALW (1 << 0)
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#define PM_PBBMASK_HRAMC1 (1 << 1)
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#define PM_PBBMASK_HMATRIX (1 << 2)
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#define PM_PBBMASK_PDCA (1 << 3)
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#define PM_PBBMASK_CRCCU (1 << 4)
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#define PM_PBBMASK_USBC (1 << 5)
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#define PM_PBBMASK_PEVC (1 << 6)
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#define PM_PBCMASK_PM (1 << 0)
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#define PM_PBCMASK_CHIPID (1 << 1)
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#define PM_PBCMASK_SCIF (1 << 2)
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#define PM_PBCMASK_FREQM (1 << 3)
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#define PM_PBCMASK_GPIO (1 << 4)
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#define PM_PBDMASK_BPM (1 << 0)
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#define PM_PBDMASK_BSCIF (1 << 1)
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#define PM_PBDMASK_AST (1 << 2)
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#define PM_PBDMASK_WDT (1 << 3)
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#define PM_PBDMASK_EIC (1 << 4)
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#define PM_PBDMASK_PICOUART (1 << 5)
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#define PM_PBADIVMASK_TC2 (1 << 0)
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#define PM_PBADIVMASK_USART0 (1 << 2)
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#define PM_PBADIVMASK_USART1 (1 << 2)
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#define PM_PBADIVMASK_USART2 (1 << 2)
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#define PM_PBADIVMASK_USART3 (1 << 2)
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#define PM_PBADIVMASK_TC3 (1 << 2)
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#define PM_PBADIVMASK_TC4 (1 << 4)
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#define PM_PBADIVMASK_TC5 (1 << 6)
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#define PM_SR_CFD (1 << 0)
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#define PM_SR_CKRDY (1 << 5)
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#define PM_SR_WAKE (1 << 8)
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enum mck_src {
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MCK_SRC_RCSYS = 0,
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MCK_SRC_OSC0,
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MCK_SRC_PLL,
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MCK_SRC_DFLL,
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MCK_SRC_RC80M,
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MCK_SRC_RCFAST,
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MCK_SRC_RC1M,
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};
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enum pm_cksel {
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PM_CKSEL_CPU = 0,
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PM_CKSEL_PBA = 2,
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PM_CKSEL_PBB,
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PM_CKSEL_PBC,
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PM_CKSEL_PBD,
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};
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/*
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* Ids are designed such that
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* PM_MASK(id/32) = (1 << id % 32)
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* would enable the peripheral clock.
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*/
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enum pm_peripheral {
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PM_PERIPHERAL_OCD = 0,
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PM_PERIPHERAL_PDCA = 32,
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PM_PERIPHERAL_FLASHCALW,
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PM_PERIPHERAL_FLASHCALW_PICORAM,
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PM_PERIPHERAL_USBC,
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PM_PERIPHERAL_CRCCU,
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PM_PERIPHERAL_APBA_BRIDGE,
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PM_PERIPHERAL_APBB_BRIDGE,
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PM_PERIPHERAL_APBC_BRIDGE,
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PM_PERIPHERAL_APBD_BRIDGE,
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PM_PERIPHERAL_AESA,
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PM_PERIPHERAL_IISC = 64,
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PM_PERIPHERAL_SPI,
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PM_PERIPHERAL_TC0,
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PM_PERIPHERAL_TC1,
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PM_PERIPHERAL_TWIM0,
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PM_PERIPHERAL_TWIS0,
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PM_PERIPHERAL_TWIM1,
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PM_PERIPHERAL_TWIS1,
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PM_PERIPHERAL_USART0,
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PM_PERIPHERAL_USART1,
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PM_PERIPHERAL_USART2,
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PM_PERIPHERAL_USART3,
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PM_PERIPHERAL_ADCIFE,
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PM_PERIPHERAL_DACC,
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PM_PERIPHERAL_ACIFC,
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PM_PERIPHERAL_GLOC,
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PM_PERIPHERAL_ABDACB,
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PM_PERIPHERAL_TRNG,
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PM_PERIPHERAL_PARC,
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PM_PERIPHERAL_CATB,
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PM_PERIPHERAL_RESERVED1,
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PM_PERIPHERAL_TWIM2,
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PM_PERIPHERAL_TWIM3,
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PM_PERIPHERAL_LCDCA,
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PM_PERIPHERAL_FLASHCALW_ALT = 96,
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PM_PERIPHERAL_HRAMC1,
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PM_PERIPHERAL_HMATRIX,
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PM_PERIPHERAL_PDCA_ALT,
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PM_PERIPHERAL_CRCCU_ALT,
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PM_PERIPHERAL_USBC_ALT,
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PM_PERIPHERAL_PEVC,
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PM_PERIPHERAL_PM = 128,
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PM_PERIPHERAL_CHIPID,
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PM_PERIPHERAL_SCIF,
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PM_PERIPHERAL_FREQM,
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PM_PERIPHERAL_GPIO,
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PM_PERIPHERAL_BPM = 160,
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PM_PERIPHERAL_BSCIF,
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PM_PERIPHERAL_AST,
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PM_PERIPHERAL_WDT,
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PM_PERIPHERAL_EIC,
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PM_PERIPHERAL_PICOUART,
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};
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BEGIN_DECLS
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void pm_select_main_clock(enum mck_src source_clock);
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void pm_enable_clock_div(enum pm_cksel sel_target, uint8_t div);
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void pm_set_divmask_clock(uint8_t mask);
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void pm_enable_peripheral_clock(enum pm_peripheral periph);
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void pm_disable_peripheral_clock(enum pm_peripheral periph);
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END_DECLS
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#endif
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