The stm32fx07 is common DesignWare IP, used in both STM32 and EFM32 chips. Rename the files to make this more clear, and easier to use in other targets.
394 lines
10 KiB
C
394 lines
10 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/usb/usbd.h>
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#include <libopencm3/usb/dwc/otg_common.h>
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#include "usb_private.h"
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#include "usb_dwc_common.h"
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/* The FS core and the HS core have the same register layout.
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* As the code can be used on both cores, the registers offset is modified
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* according to the selected cores base address. */
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#define dev_base_address (usbd_dev->driver->base_address)
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#define REBASE(x) MMIO32((x) + (dev_base_address))
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void dwc_set_address(usbd_device *usbd_dev, uint8_t addr)
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{
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REBASE(OTG_DCFG) = (REBASE(OTG_DCFG) & ~OTG_DCFG_DAD) | (addr << 4);
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}
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void dwc_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
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uint16_t max_size,
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void (*callback) (usbd_device *usbd_dev, uint8_t ep))
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{
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/*
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* Configure endpoint address and type. Allocate FIFO memory for
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* endpoint. Install callback function.
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*/
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uint8_t dir = addr & 0x80;
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addr &= 0x7f;
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if (addr == 0) { /* For the default control endpoint */
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/* Configure IN part. */
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if (max_size >= 64) {
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REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_64;
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} else if (max_size >= 32) {
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REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_32;
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} else if (max_size >= 16) {
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REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_16;
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} else {
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REBASE(OTG_DIEPCTL0) = OTG_DIEPCTL0_MPSIZ_8;
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}
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REBASE(OTG_DIEPTSIZ0) =
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(max_size & OTG_DIEPSIZ0_XFRSIZ_MASK);
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REBASE(OTG_DIEPCTL0) |=
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OTG_DIEPCTL0_EPENA | OTG_DIEPCTL0_SNAK;
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/* Configure OUT part. */
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usbd_dev->doeptsiz[0] = OTG_DIEPSIZ0_STUPCNT_1 |
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OTG_DIEPSIZ0_PKTCNT |
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(max_size & OTG_DIEPSIZ0_XFRSIZ_MASK);
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REBASE(OTG_DOEPTSIZ(0)) = usbd_dev->doeptsiz[0];
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REBASE(OTG_DOEPCTL(0)) |=
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OTG_DOEPCTL0_EPENA | OTG_DIEPCTL0_SNAK;
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REBASE(OTG_GNPTXFSIZ) = ((max_size / 4) << 16) |
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usbd_dev->driver->rx_fifo_size;
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usbd_dev->fifo_mem_top += max_size / 4;
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usbd_dev->fifo_mem_top_ep0 = usbd_dev->fifo_mem_top;
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return;
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}
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if (dir) {
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REBASE(OTG_DIEPTXF(addr)) = ((max_size / 4) << 16) |
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usbd_dev->fifo_mem_top;
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usbd_dev->fifo_mem_top += max_size / 4;
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REBASE(OTG_DIEPTSIZ(addr)) =
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(max_size & OTG_DIEPSIZ0_XFRSIZ_MASK);
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REBASE(OTG_DIEPCTL(addr)) |=
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OTG_DIEPCTL0_EPENA | OTG_DIEPCTL0_SNAK | (type << 18)
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| OTG_DIEPCTL0_USBAEP | OTG_DIEPCTLX_SD0PID
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| (addr << 22) | max_size;
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if (callback) {
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usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_IN] =
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(void *)callback;
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}
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}
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if (!dir) {
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usbd_dev->doeptsiz[addr] = OTG_DIEPSIZ0_PKTCNT |
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(max_size & OTG_DIEPSIZ0_XFRSIZ_MASK);
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REBASE(OTG_DOEPTSIZ(addr)) = usbd_dev->doeptsiz[addr];
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REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_EPENA |
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OTG_DOEPCTL0_USBAEP | OTG_DIEPCTL0_CNAK |
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OTG_DOEPCTLX_SD0PID | (type << 18) | max_size;
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if (callback) {
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usbd_dev->user_callback_ctr[addr][USB_TRANSACTION_OUT] =
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(void *)callback;
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}
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}
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}
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void dwc_endpoints_reset(usbd_device *usbd_dev)
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{
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int i;
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/* The core resets the endpoints automatically on reset. */
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usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0;
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/* Disable any currently active endpoints */
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for (i = 1; i < 4; i++) {
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if (REBASE(OTG_DOEPCTL(i)) & OTG_DOEPCTL0_EPENA) {
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REBASE(OTG_DOEPCTL(i)) |= OTG_DOEPCTL0_EPDIS;
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}
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if (REBASE(OTG_DIEPCTL(i)) & OTG_DIEPCTL0_EPENA) {
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REBASE(OTG_DIEPCTL(i)) |= OTG_DIEPCTL0_EPDIS;
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}
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}
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/* Flush all tx/rx fifos */
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REBASE(OTG_GRSTCTL) = OTG_GRSTCTL_TXFFLSH | OTG_GRSTCTL_TXFNUM_ALL
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| OTG_GRSTCTL_RXFFLSH;
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}
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void dwc_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
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{
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if (addr == 0) {
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if (stall) {
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REBASE(OTG_DIEPCTL(addr)) |= OTG_DIEPCTL0_STALL;
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} else {
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REBASE(OTG_DIEPCTL(addr)) &= ~OTG_DIEPCTL0_STALL;
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}
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}
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if (addr & 0x80) {
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addr &= 0x7F;
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if (stall) {
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REBASE(OTG_DIEPCTL(addr)) |= OTG_DIEPCTL0_STALL;
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} else {
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REBASE(OTG_DIEPCTL(addr)) &= ~OTG_DIEPCTL0_STALL;
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REBASE(OTG_DIEPCTL(addr)) |= OTG_DIEPCTLX_SD0PID;
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}
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} else {
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if (stall) {
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REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_STALL;
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} else {
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REBASE(OTG_DOEPCTL(addr)) &= ~OTG_DOEPCTL0_STALL;
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REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTLX_SD0PID;
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}
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}
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}
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uint8_t dwc_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
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{
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/* Return non-zero if STALL set. */
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if (addr & 0x80) {
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return (REBASE(OTG_DIEPCTL(addr & 0x7f)) &
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OTG_DIEPCTL0_STALL) ? 1 : 0;
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} else {
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return (REBASE(OTG_DOEPCTL(addr)) &
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OTG_DOEPCTL0_STALL) ? 1 : 0;
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}
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}
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void dwc_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
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{
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/* It does not make sense to force NAK on IN endpoints. */
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if (addr & 0x80) {
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return;
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}
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usbd_dev->force_nak[addr] = nak;
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if (nak) {
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REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_SNAK;
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} else {
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REBASE(OTG_DOEPCTL(addr)) |= OTG_DOEPCTL0_CNAK;
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}
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}
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uint16_t dwc_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
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const void *buf, uint16_t len)
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{
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const uint32_t *buf32 = buf;
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int i;
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addr &= 0x7F;
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/* Return if endpoint is already enabled. */
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if (REBASE(OTG_DIEPTSIZ(addr)) & OTG_DIEPSIZ0_PKTCNT) {
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return 0;
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}
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/* Enable endpoint for transmission. */
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REBASE(OTG_DIEPTSIZ(addr)) = OTG_DIEPSIZ0_PKTCNT | len;
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REBASE(OTG_DIEPCTL(addr)) |= OTG_DIEPCTL0_EPENA |
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OTG_DIEPCTL0_CNAK;
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/* Copy buffer to endpoint FIFO, note - memcpy does not work */
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for (i = len; i > 0; i -= 4) {
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REBASE(OTG_FIFO(addr)) = *buf32++;
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}
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return len;
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}
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uint16_t dwc_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
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void *buf, uint16_t len)
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{
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int i;
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uint32_t *buf32 = buf;
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uint32_t extra;
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/* We do not need to know the endpoint address since there is only one
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* receive FIFO for all endpoints.
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*/
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(void) addr;
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len = MIN(len, usbd_dev->rxbcnt);
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for (i = len; i >= 4; i -= 4) {
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*buf32++ = REBASE(OTG_FIFO(0));
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usbd_dev->rxbcnt -= 4;
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}
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if (i) {
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extra = REBASE(OTG_FIFO(0));
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/* we read 4 bytes from the fifo, so update rxbcnt */
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if (usbd_dev->rxbcnt < 4) {
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/* Be careful not to underflow (rxbcnt is unsigned) */
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usbd_dev->rxbcnt = 0;
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} else {
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usbd_dev->rxbcnt -= 4;
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}
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memcpy(buf32, &extra, i);
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}
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return len;
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}
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static void dwc_flush_txfifo(usbd_device *usbd_dev, int ep)
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{
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uint32_t fifo;
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/* set IN endpoint NAK */
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REBASE(OTG_DIEPCTL(ep)) |= OTG_DIEPCTL0_SNAK;
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/* wait for core to respond */
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while (!(REBASE(OTG_DIEPINT(ep)) & OTG_DIEPINTX_INEPNE)) {
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/* idle */
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}
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/* get fifo for this endpoint */
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fifo = (REBASE(OTG_DIEPCTL(ep)) & OTG_DIEPCTL0_TXFNUM_MASK) >> 22;
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/* wait for core to idle */
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while (!(REBASE(OTG_GRSTCTL) & OTG_GRSTCTL_AHBIDL)) {
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/* idle */
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}
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/* flush tx fifo */
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REBASE(OTG_GRSTCTL) = (fifo << 6) | OTG_GRSTCTL_TXFFLSH;
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/* reset packet counter */
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REBASE(OTG_DIEPTSIZ(ep)) = 0;
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while ((REBASE(OTG_GRSTCTL) & OTG_GRSTCTL_TXFFLSH)) {
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/* idle */
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}
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}
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void dwc_poll(usbd_device *usbd_dev)
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{
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/* Read interrupt status register. */
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uint32_t intsts = REBASE(OTG_GINTSTS);
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int i;
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if (intsts & OTG_GINTSTS_ENUMDNE) {
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/* Handle USB RESET condition. */
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REBASE(OTG_GINTSTS) = OTG_GINTSTS_ENUMDNE;
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usbd_dev->fifo_mem_top = usbd_dev->driver->rx_fifo_size;
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_usbd_reset(usbd_dev);
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return;
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}
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/*
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* There is no global interrupt flag for transmit complete.
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* The XFRC bit must be checked in each OTG_DIEPINT(x).
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*/
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for (i = 0; i < 4; i++) { /* Iterate over endpoints. */
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if (REBASE(OTG_DIEPINT(i)) & OTG_DIEPINTX_XFRC) {
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/* Transfer complete. */
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if (usbd_dev->user_callback_ctr[i]
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[USB_TRANSACTION_IN]) {
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usbd_dev->user_callback_ctr[i]
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[USB_TRANSACTION_IN](usbd_dev, i);
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}
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REBASE(OTG_DIEPINT(i)) = OTG_DIEPINTX_XFRC;
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}
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}
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/* Note: RX and TX handled differently in this device. */
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if (intsts & OTG_GINTSTS_RXFLVL) {
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/* Receive FIFO non-empty. */
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uint32_t rxstsp = REBASE(OTG_GRXSTSP);
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uint32_t pktsts = rxstsp & OTG_GRXSTSP_PKTSTS_MASK;
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uint8_t ep = rxstsp & OTG_GRXSTSP_EPNUM_MASK;
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if (pktsts == OTG_GRXSTSP_PKTSTS_OUT_COMP
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|| pktsts == OTG_GRXSTSP_PKTSTS_SETUP_COMP) {
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REBASE(OTG_DOEPTSIZ(ep)) = usbd_dev->doeptsiz[ep];
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REBASE(OTG_DOEPCTL(ep)) |= OTG_DOEPCTL0_EPENA |
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(usbd_dev->force_nak[ep] ?
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OTG_DOEPCTL0_SNAK : OTG_DOEPCTL0_CNAK);
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return;
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}
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if ((pktsts != OTG_GRXSTSP_PKTSTS_OUT) &&
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(pktsts != OTG_GRXSTSP_PKTSTS_SETUP)) {
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return;
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}
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uint8_t type;
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if (pktsts == OTG_GRXSTSP_PKTSTS_SETUP) {
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type = USB_TRANSACTION_SETUP;
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} else {
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type = USB_TRANSACTION_OUT;
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}
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if (type == USB_TRANSACTION_SETUP
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&& (REBASE(OTG_DIEPTSIZ(ep)) & OTG_DIEPSIZ0_PKTCNT)) {
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/* SETUP received but there is still something stuck
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* in the transmit fifo. Flush it.
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*/
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dwc_flush_txfifo(usbd_dev, ep);
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}
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/* Save packet size for dwc_ep_read_packet(). */
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usbd_dev->rxbcnt = (rxstsp & OTG_GRXSTSP_BCNT_MASK) >> 4;
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if (usbd_dev->user_callback_ctr[ep][type]) {
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usbd_dev->user_callback_ctr[ep][type] (usbd_dev, ep);
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}
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/* Discard unread packet data. */
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for (i = 0; i < usbd_dev->rxbcnt; i += 4) {
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/* There is only one receive FIFO, so use OTG_FIFO(0) */
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(void)REBASE(OTG_FIFO(0));
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}
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usbd_dev->rxbcnt = 0;
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}
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if (intsts & OTG_GINTSTS_USBSUSP) {
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if (usbd_dev->user_callback_suspend) {
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usbd_dev->user_callback_suspend();
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}
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REBASE(OTG_GINTSTS) = OTG_GINTSTS_USBSUSP;
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}
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if (intsts & OTG_GINTSTS_WKUPINT) {
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if (usbd_dev->user_callback_resume) {
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usbd_dev->user_callback_resume();
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}
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REBASE(OTG_GINTSTS) = OTG_GINTSTS_WKUPINT;
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}
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if (intsts & OTG_GINTSTS_SOF) {
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if (usbd_dev->user_callback_sof) {
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usbd_dev->user_callback_sof();
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}
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REBASE(OTG_GINTSTS) = OTG_GINTSTS_SOF;
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}
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if (usbd_dev->user_callback_sof) {
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REBASE(OTG_GINTMSK) |= OTG_GINTMSK_SOFM;
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} else {
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REBASE(OTG_GINTMSK) &= ~OTG_GINTMSK_SOFM;
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}
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}
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void dwc_disconnect(usbd_device *usbd_dev, bool disconnected)
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{
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if (disconnected) {
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REBASE(OTG_DCTL) |= OTG_DCTL_SDIS;
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} else {
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REBASE(OTG_DCTL) &= ~OTG_DCTL_SDIS;
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}
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}
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