a5966093e6
According to the reference manual, you are _forbidden_ from writing 00 to the VOS[1:0] bits in PWR_CR. Writing a 00 is automatically turned into range 2, or, 10. Attempting to then |= the bits for range 1 (01) results in the final result of choosing voltage range 3 (11). This has fairly catastrophic effects if you then attempt to switch to PLL clock at 32Mhz. Oddly, the existing code was working fine on STM32L151C6 revision W, but failing with revision V silicon. Regardless, the existing code was wrong and not following the reference manual. Further, attempting to change any power voltage range settings without the RCC enabled will have no effect, so all the higher level helper routines have added peripheral enable lines before attempting to set the range.
550 lines
12 KiB
C
550 lines
12 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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* Based on the F4 code...
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*/
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#include <libopencm3/stm32/l1/rcc.h>
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#include <libopencm3/stm32/l1/flash.h>
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#include <libopencm3/stm32/pwr.h>
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/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
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u32 rcc_ppre1_frequency = 2097000;
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u32 rcc_ppre2_frequency = 2097000;
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const clock_scale_t clock_config[CLOCK_CONFIG_END] =
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{
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{ /* 24MHz PLL from HSI */
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.pll_mul = RCC_CFGR_PLLMUL_MUL3,
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.pll_div = RCC_CFGR_PLLDIV_DIV2,
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = RANGE1,
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.flash_config = FLASH_ACR_LATENCY_1WS,
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.apb1_frequency = 24000000,
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.apb2_frequency = 24000000,
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},
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{ /* 32MHz PLL from HSI */
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.pll_mul = RCC_CFGR_PLLMUL_MUL6,
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.pll_div = RCC_CFGR_PLLDIV_DIV3,
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = RANGE1,
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.flash_config = FLASH_ACR_LATENCY_1WS,
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.apb1_frequency = 32000000,
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.apb2_frequency = 32000000,
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},
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{ /* 16MHz HSI raw */
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = RANGE1,
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.flash_config = FLASH_ACR_LATENCY_0WS,
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.apb1_frequency = 16000000,
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.apb2_frequency = 16000000,
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},
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{ /* 4MHz HSI raw */
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.hpre = RCC_CFGR_HPRE_SYSCLK_DIV4,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = RANGE1,
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.flash_config = FLASH_ACR_LATENCY_0WS,
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.apb1_frequency = 4000000,
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.apb2_frequency = 4000000,
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},
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{ /* 4MHz MSI raw */
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = RANGE1,
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.flash_config = FLASH_ACR_LATENCY_0WS,
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.apb1_frequency = 4194000,
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.apb2_frequency = 4194000,
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.msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
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},
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{ /* 2MHz MSI raw */
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.voltage_scale = RANGE1,
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.flash_config = FLASH_ACR_LATENCY_0WS,
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.apb1_frequency = 2097000,
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.apb2_frequency = 2097000,
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.msi_range = RCC_ICSCR_MSIRANGE_2MHZ,
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},
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};
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void rcc_osc_ready_int_clear(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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case MSI:
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RCC_CIR |= RCC_CIR_MSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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case MSI:
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RCC_CIR |= RCC_CIR_MSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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case MSI:
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RCC_CIR &= ~RCC_CIR_MSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(osc_t osc)
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{
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switch (osc) {
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case PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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case MSI:
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return ((RCC_CIR & RCC_CIR_MSIRDYF) != 0);
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break;
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}
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/* Shouldn't be reached. */
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return -1;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case MSI:
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while ((RCC_CR & RCC_CR_MSIRDY) == 0);
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break;
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case LSE:
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while ((RCC_CSR & RCC_CSR_LSERDY) == 0);
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break;
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case LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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void rcc_wait_for_sysclk_status(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_PLLCLK);
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break;
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case HSE:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSECLK);
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break;
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case HSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSICLK);
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break;
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case MSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_MSICLK);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case MSI:
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RCC_CR |= RCC_CR_MSION;
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break;
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case HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case LSE:
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RCC_CSR |= RCC_CSR_LSEON;
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break;
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case LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case MSI:
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RCC_CR &= ~RCC_CR_MSION;
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break;
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case HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case LSE:
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RCC_CSR &= ~RCC_CSR_LSEON;
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break;
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case LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_osc_bypass_enable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_CSR |= RCC_CSR_LSEBYP;
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break;
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case PLL:
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case HSI:
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case LSI:
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case MSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_osc_bypass_disable(osc_t osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_CSR &= ~RCC_CSR_LSEBYP;
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break;
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case PLL:
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case HSI:
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case LSI:
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case MSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
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{
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*reg |= en;
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}
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
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{
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*reg &= ~en;
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}
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
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{
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*reg |= reset;
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}
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
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{
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*reg &= ~clear_reset;
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}
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void rcc_set_sysclk_source(u32 clk)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | clk);
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}
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void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
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reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
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reg32 &= ~(1 << 16);
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reg32 |= (source << 16);
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reg32 |= (multiplier << RCC_CFGR_PLLMUL_SHIFT);
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reg32 |= (divisor << RCC_CFGR_PLLDIV_SHIFT);
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RCC_CFGR = reg32;
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}
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void rcc_set_pll_source(u32 pllsrc)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 16);
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RCC_CFGR = (reg32 | (pllsrc << 16));
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}
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void rcc_set_ppre2(u32 ppre2)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 13) | (1 << 12) | (1 << 11));
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RCC_CFGR = (reg32 | (ppre2 << 11));
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}
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void rcc_set_ppre1(u32 ppre1)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8));
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RCC_CFGR = (reg32 | (ppre1 << 8));
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}
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void rcc_set_hpre(u32 hpre)
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{
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u32 reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
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RCC_CFGR = (reg32 | (hpre << 4));
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}
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void rcc_set_rtcpre(u32 rtcpre)
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{
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u32 reg32;
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reg32 = RCC_CR;
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reg32 &= ~((1 << 30) | (1 << 29));
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RCC_CR = (reg32 | (rtcpre << 29));
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}
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u32 rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return ((RCC_CFGR & 0x000c) >> 2);
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}
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void rcc_rtc_select_clock(u32 clock)
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{
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RCC_CSR &= ~(RCC_CSR_RTCSEL_MASK << RCC_CSR_RTCSEL_SHIFT);
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RCC_CSR |= (clock << RCC_CSR_RTCSEL_SHIFT);
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}
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void rcc_clock_setup_msi(const clock_scale_t *clock)
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{
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/* Enable internal multi-speed oscillator. */
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u32 reg = RCC_ICSCR;
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reg &= ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT);
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reg |= (clock->msi_range << RCC_ICSCR_MSIRANGE_SHIFT);
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RCC_ICSCR = reg;
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rcc_osc_on(MSI);
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rcc_wait_for_osc_ready(MSI);
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/* Select MSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_MSICLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre1(clock->ppre1);
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rcc_set_ppre2(clock->ppre2);
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rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
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pwr_set_vos_scale(clock->voltage_scale);
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// I guess this should be in the settings?
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flash_64bit_enable();
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flash_prefetch_enable();
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/* Configure flash settings. */
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flash_set_ws(clock->flash_config);
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/* Set the peripheral clock frequencies used. */
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rcc_ppre1_frequency = clock->apb1_frequency;
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rcc_ppre2_frequency = clock->apb2_frequency;
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}
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void rcc_clock_setup_hsi(const clock_scale_t *clock)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre1(clock->ppre1);
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rcc_set_ppre2(clock->ppre2);
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rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
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pwr_set_vos_scale(clock->voltage_scale);
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|
|
|
// I guess this should be in the settings?
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|
flash_64bit_enable();
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|
flash_prefetch_enable();
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|
/* Configure flash settings. */
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|
flash_set_ws(clock->flash_config);
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|
|
|
/* Set the peripheral clock frequencies used. */
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|
rcc_ppre1_frequency = clock->apb1_frequency;
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|
rcc_ppre2_frequency = clock->apb2_frequency;
|
|
}
|
|
|
|
void rcc_clock_setup_pll(const clock_scale_t *clock)
|
|
{
|
|
/* Enable internal high-speed oscillator. */
|
|
rcc_osc_on(HSI);
|
|
rcc_wait_for_osc_ready(HSI);
|
|
|
|
/*
|
|
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
|
* Do this before touching the PLL (TODO: why?).
|
|
*/
|
|
rcc_set_hpre(clock->hpre);
|
|
rcc_set_ppre1(clock->ppre1);
|
|
rcc_set_ppre2(clock->ppre2);
|
|
|
|
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
|
|
pwr_set_vos_scale(clock->voltage_scale);
|
|
|
|
// I guess this should be in the settings?
|
|
flash_64bit_enable();
|
|
flash_prefetch_enable();
|
|
/* Configure flash settings. */
|
|
flash_set_ws(clock->flash_config);
|
|
|
|
rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, clock->pll_div);
|
|
|
|
/* Enable PLL oscillator and wait for it to stabilize. */
|
|
rcc_osc_on(PLL);
|
|
rcc_wait_for_osc_ready(PLL);
|
|
|
|
/* Select PLL as SYSCLK source. */
|
|
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
|
|
|
|
/* Set the peripheral clock frequencies used. */
|
|
rcc_ppre1_frequency = clock->apb1_frequency;
|
|
rcc_ppre2_frequency = clock->apb2_frequency;
|
|
}
|