49 lines
1.4 KiB
Plaintext
49 lines
1.4 KiB
Plaintext
------------------------------------------------------------------------------
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README
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------------------------------------------------------------------------------
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This program exercises the SSP1 peripheral on Jellybean's LPC43xx.
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Jellybean (connector)
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P9 SPI
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|-----------------|
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| Pin2 Pin4 Pin6 |
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||------| |
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|| Pin1 |Pin3 Pin5 |
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||------|----------|
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|-------|
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SSP1_MISO: Jellybean P9 SPI Pin6
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SSP1_MOSI: Jellybean P9 SPI Pin4
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SSP1_SCK: Jellybean P9 SPI Pin2
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SSP1_SSEL: Jellybean P9 SPI Pin3
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GND: Can be connected to P12 SD Pin1
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PCLK clock source is PLL1 288MHz (from IRC 96MHz boot from SPIFI)
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Freq = PCLK / (CPSDVSR * [SCR+1]).
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By default (CPSDVSR=0 => Means MAX Divisor)
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SSP1->CR0->SCR = 0x00 => CLK Freq 1.126MHz
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SSP1->CR0->SCR = 0x01 => MOSI Freq 566.9KHz
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...
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Test Oscilloscpe:
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SCR=0, CPSDVSR=32 => CLK 9.025MHz
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SCR=1, CPSDVSR=2 => CLK 73MHz
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SCR=2, CPSDVSR=2 => CLK 49MHz
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SCR=4, CPSDVSR=2 => CLK 29MHz
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SCR=8, CPSDVSR=2 => CLK 16MHz
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SCR=16, CPSDVSR=2 => CLK 8.5MHz
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SCR=32, CPSDVSR=2 => CLK 4.386MHz
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SCR=64, CPSDVSR=2 => CLK 2.227MHz
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SCR=1, CPSDVSR=64 => CLK 2.262MHz
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Theory:
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SCR=0, CPSDVSR=32 => 288MHz / (32*(0+1) = 9MHz
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SCR=1, CPSDVSR=2 => 288MHz / (2*(1+1) = 72MHz
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SCR=4, CPSDVSR=2 => 288MHz / (2*(4+1) = 28.8MHz
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SCR=32, CPSDVSR=2 => 288MHz / (2*(32+1) = 4.364MHz
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SCR=64, CPSDVSR=2 => 288MHz / (2*(64+1)) = 2.2154MHz
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SCR=128, CPSDVSR=2 => 288MHz / (2*(128+1)) = 1.116MHz
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SCR=1, CPSDVSR=64 => 288MHz / (64*(1+1)) = 2.25MHz
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