7df63fcae0
Added --terse and --mailback options to the make stylecheck target. It also does continue even if it enounters a possible error. We decided on two exceptions from the linux kernel coding standard: - Empty wait while loops may end with ; on the same line. - All blocks after while, if, for have to be in brackets even if they only contain one statement. Otherwise it is easy to introduce an error. Checkpatch needs to be adapted to reflect those changes.
66 lines
2.5 KiB
C
66 lines
2.5 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC17XX_MEMORYMAP_H
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#define LPC17XX_MEMORYMAP_H
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#include <libopencm3/cm3/common.h>
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/* --- LPC17XX specific peripheral definitions ----------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE_APB0 0x40000000
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#define PERIPH_BASE_APB1 0x40080000
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#define PERIPH_BASE_AHB 0x20000000
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/* Register boundary addresses */
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/* APB0 */
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#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000)
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#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
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#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000)
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#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000)
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#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000)
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/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */
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#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000)
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#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
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#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
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#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
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#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000)
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#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
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#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
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#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)
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#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000)
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#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000)
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#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000)
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#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000)
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#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000)
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/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */
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#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000)
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/* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */
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/* AHB */
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#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000)
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#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020)
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#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040)
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#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060)
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#define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080)
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#endif
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