119 lines
4.1 KiB
C
119 lines
4.1 KiB
C
/** @defgroup dac_defines DAC Defines
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*
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* @brief <b>Defined Constants and Types for the STM32F0xx Digital to Analog
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* Converter</b>
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*
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* @ingroup STM32F0xx_defines
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*
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* @version 1.0.0
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*
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* @date 11 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_DAC_H
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#define LIBOPENCM3_DAC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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/*****************************************************************************/
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/* Module definitions */
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/*****************************************************************************/
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#define DAC DAC_BASE
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/*****************************************************************************/
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/* Register definitions */
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/*****************************************************************************/
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#define DAC_CR MMIO32(DAC_BASE + 0x00)
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#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
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#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
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#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
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#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
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#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
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#define DAC_SR MMIO32(DAC_BASE + 0x34)
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/*****************************************************************************/
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/* Register values */
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/*****************************************************************************/
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/* DAC_CR Values ------------------------------------------------------------*/
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#define DAC_CR_DMAUDRIE1 (1 << 13)
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#define DAC_CR_DMAEN1 (1 << 12)
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#define DAC_CR_TSEL1_SHIFT 3
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#define DAC_CR_TSEL1 (7 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_TIM6_TRGO (0 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_TIM8_TRGO (1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_TIM7_TRGO (2 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_TIM5_TRGO (3 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_TIM2_TRGO (4 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_TIM4_TRGO (5 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_EXT_9 (6 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_SWTRG (7 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TEN1 (1 << 2)
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#define DAC_CR_BOFF1 (1 << 1)
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#define DAC_CR_EN1 (1 << 0)
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/* DAC_SWTRIGR Values -------------------------------------------------------*/
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#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
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/* DAC_DHR12R1 Values -------------------------------------------------------*/
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#define DAC_DHR12R1_DACC1DHR 0xFFF
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/* DAC_DHR12L1 Values -------------------------------------------------------*/
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#define DAC_DHR12L1_DACC1DHR (0xFFF << 4)
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/* DAC_DHR8R1 Values --------------------------------------------------------*/
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#define DAC_DHR8R1_DACC1DHR 0xFF
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/* DAC_DOR1 Values ----------------------------------------------------------*/
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#define DAC_DOR1_DACC1DOR 0xFFF
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/* DAC_SR Values ------------------------------------------------------------*/
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#define DAC_SR_DMAUDR1 (1 << 13)
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/*****************************************************************************/
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/* API definitions */
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/*****************************************************************************/
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/*****************************************************************************/
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/* API Functions */
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/*****************************************************************************/
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BEGIN_DECLS
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END_DECLS
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#endif
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