ad5ec6af08
This adds the "volatile" keyword to all the inline assembly. gcc docs say "You can prevent an asm instruction from being deleted by writing the keyword volatile after the asm.". Testing (see comments of github issue #475) shows that indeed gcc can remove some inline asm, in at least this situation: -multiple calls to cm_is_masked_interrupts() in the same scope/context - -Os or -O2 optimization This is problem because the value of PRIMASK could change between two calls to cm_is_masked_interrupts(). Adding the volatile keyword fixes this, and probably costs less than adding a full barrier (like adding "memory" to the clobber list).
282 lines
8.3 KiB
C
282 lines
8.3 KiB
C
/** @defgroup CM3_cortex_defines Cortex Core Defines
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*
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* @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
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*
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* @ingroup CM3_defines
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*
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* @version 1.0.0
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CORTEX_H
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#define LIBOPENCM3_CORTEX_H
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/**@{*/
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#include <stdbool.h>
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Enable interrupts
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*
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* Disable the interrupt mask and enable interrupts globally
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*/
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static inline void cm_enable_interrupts(void)
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{
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__asm__ volatile ("CPSIE I\n");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Disable interrupts
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*
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* Mask all interrupts globally
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*/
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static inline void cm_disable_interrupts(void)
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{
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__asm__ volatile ("CPSID I\n");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Enable faults
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*
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* Disable the HardFault mask and enable fault interrupt globally
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*/
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static inline void cm_enable_faults(void)
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{
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__asm__ volatile ("CPSIE F\n");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Disable faults
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*
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* Mask the HardFault interrupt globally
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*/
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static inline void cm_disable_faults(void)
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{
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__asm__ volatile ("CPSID F\n");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Check if interrupts are masked
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*
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* Checks, if interrupts are masked (disabled).
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*
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* @returns true, if interrupts are disabled.
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*/
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__attribute__((always_inline))
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static inline bool cm_is_masked_interrupts(void)
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{
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register uint32_t result;
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__asm__ volatile ("MRS %0, PRIMASK" : "=r" (result));
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return result;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Check if Fault interrupt is masked
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*
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* Checks, if HardFault interrupt is masked (disabled).
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*
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* @returns bool true, if HardFault interrupt is disabled.
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*/
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__attribute__((always_inline))
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static inline bool cm_is_masked_faults(void)
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{
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register uint32_t result;
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__asm__ volatile ("MRS %0, FAULTMASK" : "=r" (result));
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return result;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Mask interrupts
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*
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* This function switches the mask of the interrupts. If mask is true, the
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* interrupts will be disabled. The result of this function can be used for
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* restoring previous state of the mask.
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*
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* @param[in] mask bool New state of the interrupt mask
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* @returns bool old state of the interrupt mask
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*/
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__attribute__((always_inline))
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static inline bool cm_mask_interrupts(bool mask)
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{
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register bool old;
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__asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old));
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__asm__ __volatile__("" : : : "memory");
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__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
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return old;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Mask HardFault interrupt
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*
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* This function switches the mask of the HardFault interrupt. If mask is true,
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* the HardFault interrupt will be disabled. The result of this function can be
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* used for restoring previous state of the mask.
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*
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* @param[in] mask bool New state of the HardFault interrupt mask
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* @returns bool old state of the HardFault interrupt mask
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*/
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__attribute__((always_inline))
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static inline bool cm_mask_faults(bool mask)
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{
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register bool old;
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__asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old));
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__asm__ __volatile__ ("" : : : "memory");
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__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
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return old;
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}
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/**@}*/
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/*===========================================================================*/
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/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
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*
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* @brief Atomic operation support
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*
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* @ingroup CM3_cortex_defines
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*/
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/**@{*/
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#if !defined(__DOXYGEN__)
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/* Do not populate this definition outside */
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static inline bool __cm_atomic_set(bool *val)
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{
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return cm_mask_interrupts(*val);
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}
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#define __CM_SAVER(state) \
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__val = state, \
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__save __attribute__((__cleanup__(__cm_atomic_set))) = \
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__cm_atomic_set(&__val)
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#endif /* !defined(__DOXYGEN) */
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Atomic Declare block
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*
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* This macro disables interrupts for the next command or block of code. The
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* interrupt mask is automatically restored after exit of the boundary of the
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* code block. Therefore restore of interrupt is done automatically after call
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* of return or goto control sentence jumping outside of the block.
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*
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* @warning The usage of sentences break or continue is prohibited in the block
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* due to implementation of this macro!
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*
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* @note It is safe to use this block inside normal code and in interrupt
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* routine.
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*
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* @example 1: Basic usage of atomic block
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*
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* @code
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* uint64_t value; // This value is used somewhere in interrupt
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*
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* ...
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*
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* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
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* value = value * 1024 + 651; // access value as atomic
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* } // interrupts is restored automatically
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* @endcode
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*
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* @example 2: Use of return inside block:
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*
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* @code
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* uint64_t value; // This value is used somewhere in interrupt
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*
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* ...
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*
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* uint64_t allocval(void)
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* {
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* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
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* value = value * 1024 + 651; // do long atomic operation
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* return value; // interrupts is restored automatically
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* }
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* }
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* @endcode
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*/
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#if defined(__DOXYGEN__)
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#define CM_ATOMIC_BLOCK()
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#else /* defined(__DOXYGEN__) */
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#define CM_ATOMIC_BLOCK() \
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for (bool __CM_SAVER(true), __my = true; __my; __my = false)
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#endif /* defined(__DOXYGEN__) */
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/*---------------------------------------------------------------------------*/
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/** @brief Cortex M Atomic Declare context
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*
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* This macro disables interrupts in the current block of code from the place
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* where it is defined to the end of the block. The interrupt mask is
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* automatically restored after exit of the boundary of the code block.
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* Therefore restore of interrupt is done automatically after call of return,
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* continue, break, or goto control sentence jumping outside of the block.
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*
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* @note This function is intended for use in for- cycles to enable the use of
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* break and contine sentences inside the block, and for securing the atomic
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* reader-like functions.
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*
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* @note It is safe to use this block inside normal code and in interrupt
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* routine.
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*
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* @example 1: Basic usage of atomic context
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*
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* @code
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* uint64_t value; // This value is used somewhere in interrupt
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*
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* ...
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*
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* for (int i=0;i < 100; i++) {
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* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
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* value += 100; // access value as atomic
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* if ((value % 16) == 0) {
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* break; // restore interrupts and break cycle
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* }
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* } // interrupts is restored automatically
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* @endcode
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*
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* @example 2: Usage of atomic context inside atomic reader fcn.
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*
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* @code
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* uint64_t value; // This value is used somewhere in interrupt
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*
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* ...
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*
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* uint64_t getnextval(void)
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* {
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* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
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* value = value + 3; // do long atomic operation
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* return value; // interrupts is restored automatically
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* }
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* @endcode
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*/
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#if defined(__DOXYGEN__)
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#define CM_ATOMIC_CONTEXT()
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#else /* defined(__DOXYGEN__) */
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#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true)
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#endif /* defined(__DOXYGEN__) */
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/**@}*/
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#endif
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