b385b7a172
Add initial support for the NXP LPC13XX family of ARM Cortex-M3 devices, including the LPC1311, LPC1313, LPC1342, or LPC1343. This should re-use parts of our generic Cortex-M3 stuff (which is gradually moved into cm3/ subdirs) where possible.
59 lines
2.2 KiB
C
59 lines
2.2 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC13XX_MEMORYMAP_H
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#define LPC13XX_MEMORYMAP_H
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#include <cm3/common.h>
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/* --- LPC13XX specific peripheral definitions ----------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE_APB 0x40000000
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#define PERIPH_BASE_AHB 0x50000000
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/* Register boundary addresses */
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/* APB */
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#define I2C_BASE (PERIPH_BASE_APB + 0x00000)
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#define WDT_BASE (PERIPH_BASE_APB + 0x04000)
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#define UART_BASE (PERIPH_BASE_APB + 0x08000)
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#define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000)
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#define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000)
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#define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000)
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#define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000)
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#define ADC_BASE (PERIPH_BASE_APB + 0x1c000)
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#define USB_BASE (PERIPH_BASE_APB + 0x20000)
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/* PERIPH_BASE_APB + 0x28000 (0x4002 8000 - 0x4003 7FFF): Reserved */
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#define PMU_BASE (PERIPH_BASE_APB + 0x38000)
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#define FLASH_BASE (PERIPH_BASE_APB + 0x3c000)
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#define SSP_BASE (PERIPH_BASE_APB + 0x40000)
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#define IOCONFIG_BASE (PERIPH_BASE_APB + 0x44000)
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#define SYSCTRL_BASE (PERIPH_BASE_APB + 0x48000)
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/* PERIPH_BASE_APB + 0x4c000 (0x4004 c000 - 0x4007 FFFF): Reserved */
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/* AHB */
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#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x00000)
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#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x10000)
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#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x20000)
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#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x30000)
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/* PERIPH_BASE_AHB + 0x40000 (0x5004 0000 - 0x501F FFFF): Reserved */
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#endif
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