7957cffaa3
Add an abstraction layer to handle the clock control for the run time clock on LM4F (RCC). Sleep and deep-sleep clock configuration is not handled. Complete documentation for the clock control API is included in doxygen-style comments, and is included in [doc]. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Conflicts: lib/lm4f/Makefile
127 lines
3.8 KiB
C
127 lines
3.8 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @defgroup rcc_defines RCC Defines
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*
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* @ingroup LM4F_defines
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*
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* \brief <b>Defined Constants and Types for the LM4F Clock control API</b>
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* @{
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*/
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#ifndef LM4F_RCC_H
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#define LM4F_RCC_H
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#include <libopencm3/lm4f/systemcontrol.h>
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/**
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* \brief Oscillator source values
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*
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* Possible values of the oscillator source.
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*/
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typedef enum {
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OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC,
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OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC,
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OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4,
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OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K,
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OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768,
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} osc_src_t;
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/**
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* \brief PWM clock divisor values
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*
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* Possible values of the binary divisor used to predivide the system clock down
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* for use as the timing reference for the PWM module.
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*/
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typedef enum {
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PWMDIV_2 = SYSCTL_RCC_PWMDIV_2,
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PWMDIV_4 = SYSCTL_RCC_PWMDIV_4,
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PWMDIV_8 = SYSCTL_RCC_PWMDIV_8,
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PWMDIV_16 = SYSCTL_RCC_PWMDIV_16,
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PWMDIV_32 = SYSCTL_RCC_PWMDIV_32,
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PWMDIV_64 = SYSCTL_RCC_PWMDIV_64,
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} pwm_clkdiv_t;
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/**
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* \brief Predefined crystal values
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*
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* Predefined crystal values for the XTAL field in SYSCTL_RCC.
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* Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and
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* SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock
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* of 400MHz.
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*/
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typedef enum {
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XTAL_4M = SYSCTL_RCC_XTAL_4M,
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XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096,
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XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152,
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XTAL_5M = SYSCTL_RCC_XTAL_5M,
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XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12,
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XTAL_6M = SYSCTL_RCC_XTAL_6M,
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XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144,
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XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728,
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XTAL_8M = SYSCTL_RCC_XTAL_8M,
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XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192,
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XTAL_10M = SYSCTL_RCC_XTAL_10M,
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XTAL_12M = SYSCTL_RCC_XTAL_12M,
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XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288,
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XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56,
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XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818,
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XTAL_16M = SYSCTL_RCC_XTAL_16M,
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XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384,
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XTAL_18M = SYSCTL_RCC_XTAL_18M,
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XTAL_20M = SYSCTL_RCC_XTAL_20M,
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XTAL_24M = SYSCTL_RCC_XTAL_24M,
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XTAL_25M = SYSCTL_RCC_XTAL_25M,
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} xtal_t;
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/**
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* @}
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*/
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/* =============================================================================
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* Function prototypes
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* ---------------------------------------------------------------------------*/
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BEGIN_DECLS
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/* Low-level clock API */
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void rcc_configure_xtal(xtal_t xtal);
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void rcc_disable_main_osc(void);
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void rcc_disable_interal_osc(void);
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void rcc_enable_main_osc(void);
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void rcc_enable_interal_osc(void);
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void rcc_enable_rcc2(void);
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void rcc_pll_off(void);
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void rcc_pll_on(void);
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void rcc_set_osc_source(osc_src_t src);
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void rcc_pll_bypass_disable(void);
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void rcc_pll_bypass_enable(void);
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void rcc_set_pll_divisor(u8 div400);
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void rcc_set_pwm_divisor(pwm_clkdiv_t div);
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void rcc_usb_pll_off(void);
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void rcc_usb_pll_on(void);
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void rcc_wait_for_pll_ready(void);
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/* High-level clock API */
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void rcc_change_pll_divisor(u8 plldiv400);
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u32 rcc_get_system_clock_frequency(void);
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void rcc_sysclk_config(osc_src_t src, xtal_t xtal, u8 pll_div400);
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END_DECLS
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#endif /* LM4F_RCC_H */
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